Thick metal layer integrated process flow to improve power delivery and mechanical buffering
View Patent ↗A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
1. An apparatus comprising:
first and second Controlled Collapse Chip Connection bumps;
a unitary first metal layer coupled to the first and second bumps, the first metal layer being formed in a trench of a dielectric layer, the first metal layer being coupled to a top metal layer of an integrated circuit die, the first metal layer being adapted to transfer current from the first and second bumps to the top metal layer of the integrated circuit die; and
a unitary second metal layer over the first metal layer, the second metal layer being coupled to the first bump, a third bump and the first metal layer, the second metal layer being adapted to transfer current from the first and third bumps to the first metal layer.
2. The apparatus of claim 1 , wherein the third bump is a Controlled Collapse Chip Connection bump.
3. The apparatus of claim 1 , wherein the first and second bumps are coupled to first and second solder bumps of a substrate.
4. The apparatus of claim 1 , wherein the first metal layer is about 10 to 50 microns thick.
5. The apparatus of claim 1 , wherein the first metal layer comprises electroplated copper.
6. The apparatus of claim 1 , wherein the first metal layer is deposited in vias over a first base layer metallization, which is deposited over the top metal layer of the integrated circuit die.
7. The apparatus of claim 1 , further comprising a first dielectric layer enclosing the first metal layer.
8. The apparatus of claim 7 , wherein the first dielectric layer comprises a self-planarizing, photo-definable polymer.
9. The apparatus of claim 7 , wherein the first dielectric layer comprises a self-planarizing, non-photo-definable polymer.
10. The apparatus of claim 1 , wherein the second metal layer is orthogonal to the first metal layer.
11. The apparatus of claim 1 , further comprising a unitary diffusion barrier over and on sides of the first metal layer.
12. The apparatus of claim 3 , wherein current from the substrate is spread to both of the first and second solder bumps and then to both of the first and second Controlled Collapse Chip Connection bumps.
13. An apparatus comprising:
first and second connection means;
a unitary first metal layer coupled to the first and second connection means, the first metal layer being formed in a trench of a dielectric layer, the first metal layer being coupled to a top metal layer of an integrated circuit die, the first metal layer being adapted to transfer current from the first and second connection means to the top metal layer of the integrated circuit die; and
a unitary second metal layer over the first metal layer, the second metal layer being coupled to the first connection means, a third connection means and the first metal layer, the second metal layer being adapted to transfer current from the first and third connection means to the first metal layer.
14. The apparatus of claim 13 , wherein the first, second, and third connection means are Controlled Collapse Chip Connection bumps.
15. The apparatus of claim 13 , wherein the first and second connection means are coupled to first and second solder bumps of a substrate.
16. The apparatus of claim 13 , wherein the first metal layer is deposited in vias over a first base layer metallization, which is deposited over the top metal layer of the integrated circuit die.
17. The apparatus of claim 13 , further comprising dielectric layering means enclosing the first metal layer.
18. The apparatus of claim 17 , wherein the first dielectric layer means comprises self-planarizing, photo-definable polymer.
19. The apparatus of claim 17 , wherein the first dielectric layer means comprises self-planarizing, non-photo-definable polymer.
20. The apparatus of claim 17 , wherein the second metal layer is orthogonal to the first metal layer.
21. The apparatus of claim 17 , wherein the first dielectric layer means comprises self-planarizing, photo-definable polymer.
22. The apparatus of claim 17 , wherein the first dielectric layer means comprises self-planarizing, non-photo-definable polymer.
23. The apparatus of claim 17 , further comprising diffusion barrier means over and on sides of the first layer means.
24. An apparatus comprising:
first and second connection means;
first unitary layer means coupled to the first and second connection means, the first layer means being formed in a trench of a dielectric layer, the first layer means being coupled to a top metal layer of an integrated circuit die, the first layer means being adapted to transfer current from the first and second connection means to the top metal layer of the integrated circuit die; and
second unitary layer means over and orthogonal to the first layer means, the second layer means layer being coupled to the first connection means, a third connection means and the first layer means, the second layer means being adapted to transfer current from the first and third connection means to the first layer means.
25. The apparatus of claim 24 , wherein the first, second, and third connection means are Controlled Collapse Chip Connection bumps.
26. The apparatus of claim 24 , wherein the first and second connection means are coupled to first and second solder bumps of a substrate.
27. The apparatus of claim 24 , wherein the first layer means is deposited in vias over a first base layer metallization, which is deposited over the top metal layer of the integrated circuit die.
28. The apparatus of claim 24 , further comprising dielectric layering means enclosing the first metal layer.