Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
View Patent ↗Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.
1. An apparatus comprising:
a voltage reference generator to generate a voltage reference; and
a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event, wherein the event includes exceeding a predetermined bit error rate, wherein the dynamic voltage reference control unit is controllable by software.
2. The apparatus of claim 1 , further comprising:
a dynamic random access memory (DRAM); and
a dual in-line memory module (DIMM), coupled with the DRAM, having the voltage reference generator to provide the dynamically adjusted voltage reference level to the DRAM.
3. The apparatus of claim 2 , wherein the voltage reference generator comprises:
a variable resistor ladder to adjust the level of the voltage reference; and
a voltage follower, coupled with the variable resistor ladder, to buffer the voltage reference to the DRAM.
4. The apparatus of claim 1 , wherein the dynamic voltage reference control unit is operable by a basic input/output system (BIOS).
5. The apparatus of claim 4 , wherein the dynamic voltage reference control unit is operable at boot time via the BIOS.
6. The apparatus of claim 1 , wherein the event includes a timing failure in an input/output system.
7. An apparatus comprising:
a voltage reference generator to generate a voltage reference, the voltage reference generator having a voltage follower or coupled to it; and
a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event.
8. The apparatus of claim 7 , further comprising:
a dual in-line memory module (DIMM), coupled with a DRAM, having the voltage reference generator to provide the dynamically adjusted voltage reference level to the DRAM.
9. The apparatus of claim 8 , wherein the voltage reference generator comprises:
a variable resistor ladder to adjust the level of the voltage reference, and
wherein the voltage follower is coupled with the variable resistor ladder to buffer the voltage reference to the DRAM.
10. The apparatus of claim 7 , wherein the dynamic voltage reference control unit is controlled by software.
11. The apparatus of claim 7 , wherein the dynamic voltage reference control unit is operable by a basic input/output system (BIOS).
12. The apparatus of claim 11 , wherein the dynamic voltage reference control unit is operable at boot time via the BIOS.
13. An apparatus comprising:
a voltage reference generator to generate a voltage reference;
a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event; and
a dual in-line memory module (DIMM), coupled with a DRAM, having the voltage reference generator to provide the dynamically adjusted voltage reference level to the DRAM.
14. The apparatus of claim 13 , wherein the voltage reference generator comprises:
a variable resistor ladder to adjust the level of the voltage reference; and
a voltage follower, coupled with the variable resistor ladder, to buffer the voltage reference to the DRAM.
15. The apparatus of claim 13 , wherein the dynamic voltage reference control unit is controlled by software.
16. The apparatus of claim 13 , wherein the dynamic voltage reference control unit is operable by a basic input/output system (BIOS).
17. The apparatus of claim 13 , wherein the event includes a timing failure in an input/output system.
18. The apparatus pf claim 13 , wherein the event includes exceeding a predetermined bit error rate.
19. The apparatus of claim 1 , wherein the dynamic voltage reference control unit includes a compensation circuit having a feedback loop to adjust a voltage level of the voltage reference.