Apparatus for low power write and read operations for resistive memory
Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
1. An apparatus comprising:
a resistive memory cell coupled to a bit line and a select line;
a first pass-gate coupled to the bit line;
a second pass-gate coupled to the select line;
a differential write driver to receive a differential input and to drive a differential output to the first and second pass-gates, wherein the differential write driver to cause a first output of the differential output to have a different drive strength than a second output of the differential output, wherein the differential write driver comprises an adjustable n-type current source; and
a variable voltage generator to provide a bias for the adjustable n-type current source according to the first or second outputs or both, wherein the variable voltage generator comprises:
a multiplexer controllable by the first or second outputs or both; and
a voltage divider to provide a plurality of voltages of different levels to the multiplexer.
2. The apparatus of claim 1 , wherein the differential write driver comprises an adjustable p-type current source.
3. The apparatus of claim 2 further comprises a variable voltage generator to provide a bias for the adjustable p-type current source according to the first or second outputs or both.
4. The apparatus of claim 1 further comprises a multiplexer operable by an input data, the multiplexer to provide a control signal to the first and second pass-gates according to logic level of the input data.
5. The apparatus of claim 4 , wherein the multiplexer to receive at least two inputs of different pulse widths.
6. The apparatus of claim 5 further comprises logic to adjust pulse widths of the at least two inputs.
7. The apparatus of claim 6 , wherein the at least two inputs are first and second write enable pulses, the first write enable pulse for controlling duration of writing a logical high to the resistive memory cell, and the second write enable pulse for controlling duration of writing a logical low to the resistive memory cell.
8. The apparatus of claim 1 , wherein the resistive memory cell is at least one of: STT-MRAM; ReRAM; PCM; or CBRAM.
9. The apparatus of claim 1 , wherein the resistive memory cell is an STT-MRAM bit-cell which comprises:
a select transistor controllable by a word line; and
a magnetic tunnel junction (MTJ) device coupled in series with the select transistor.
10. A system comprising:
a processor core;
a memory coupled to the processor core, wherein the memory comprising:
a resistive memory cell coupled to a bit line and a select line;
a first pass-gate coupled to the bit line;
a second pass-gate coupled to the select line; and
a differential write driver to receive a differential input and to drive a differential output to the first and second pass-gates, wherein the differential write driver to cause a first output of the differential output to have a different drive strength than a second output of the differential output;
a multiplexer operable by an input data, the multiplexer to provide a control signal to the first and second pass-gates according to logic level of the input data, wherein the multiplexer is to receive at least two inputs of different pulse widths; and
a wireless interface to allow the processor core to communicate with another device.
11. The system of claim 10 , wherein the differential write driver comprises an adjustable p-type current source.
12. The system of claim 11 further comprises a variable voltage generator to provide a bias for the adjustable p-type current source according to the first or second outputs or both.
13. The system of claim 10 , wherein the differential write driver comprises an adjustable n-type current source.
14. The system of claim 13 further comprises a variable voltage generator to provide a bias for the adjustable n-type current source according to the first or second outputs or both.
15. An apparatus comprising:
a resistive memory cell coupled to a bit line and a select line; and
a differential write driver to receive a differential input and to drive a differential output to first and second pass-gates, wherein the first and second pass-gates are coupled to the resistive memory cell,
wherein the differential write driver to cause a first output of the differential output to have a different drive strength than a second output of the differential output.
16. The apparatus of claim 15 , wherein the differential write driver comprises an adjustable n-type current source.
17. The apparatus of claim 16 further comprises a variable voltage generator to provide a bias for the adjustable n-type current source according to the first or second outputs or both.