DRAM data path sharing via a split local data bus
View Patent ↗Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
1. A memory device, comprising:
a first bus comprising a first set of lines and a second set of lines;
a second bus split into a first part and a second part; and
an element configurable to transmit a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.
2. The memory device of claim 1 , wherein the first bus is a global data bus, and wherein the second bus is a local data bus.
3. The memory device of claim 2 , wherein a width of the local data bus is half of a prefetch width of the memory device.
4. The memory device of claim 2 , wherein the local data bus is configurable to separate logically consecutive data for directing data to the global data bus.
5. The memory device of claim 2 , wherein a first section and a second section of an array tile are located in between the first set of lines of the global data bus and the second set of lines of the global data bus, and wherein the local data bus is located in between the first section and the second section of the array tile.
6. The memory device of claim 1 , wherein the memory device comprises at least one of a volatile or a nonvolatile memory device.
7. A memory device, comprising:
a first bus comprising a first set of lines and a second set of lines;
a second bus split into a first part and a second part; and
an element configurable to transmit a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first part of the second bus and the second part of the second bus are both located in between the first set of lines and the second set of lines of the first bus.
8. The memory device of claim 7 , wherein the element is a decoder.
9. A method, comprising:
directing signals to a first bus comprising a first set of lines and a second set of lines from a second bus that is split into a first part and a second part; and
transmitting, via an element, a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.
10. The method of claim 9 , wherein the first bus is a global data bus, and wherein the second bus is a local data bus.
11. The method of claim 10 , wherein a width of the local data bus is half of a prefetch width of a memory device.
12. The method of claim 10 , wherein the local data bus is configurable to separate logically consecutive data for directing data to the global data bus.
13. A computational device, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising:
a first bus comprising a first set of lines and a second set of lines;
a second bus split into a first part and a second part; and
an element configurable to transmit a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first set of signals select one half of a word line, and wherein the second set of signals select another half of the word line.
14. The computational device of claim 13 , wherein the first bus is a global data bus, and wherein the second bus is a local data bus.
15. The computational device of claim 14 , wherein a width of the local data bus is half of a prefetch width of the memory device.
16. The computational device of claim 14 , wherein the local data bus is configurable to separate logically consecutive data for directing data to the global data bus.
17. A method, comprising:
directing signals to a first bus comprising a first set of lines and a second set of lines from a second bus that is split into a first part and a second part; and
transmitting, via an element, a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first part of the second bus and the second part of the second bus are both located in between the first set of lines and the second set of lines of the first bus.
18. The method of claim 17 , wherein the element is a decoder.
19. A computational device, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising:
a first bus comprising a first set of lines and a second set of lines;
a second bus split into a first part and a second part; and
an element configurable to transmit a first set of signals along the first part of the second bus to the first set of lines of the first bus, and a second set of signals along the second part of the second bus to the second set of lines of the first bus, wherein the first part of the second bus and the second part of the second bus are both located in between the first set of lines and the second set of lines of the first bus.
20. The computational device of claim 19 , wherein the element is a decoder.