Memory power delivery noise suppression
View Patent ↗In some embodiments a voltage regulator provides an operation voltage to a memory system and a transient voltage supply adjusts the operation voltage provided by the voltage regulator during transient events of the memory system. Additionally, the voltage supply may adjust the operation voltage provided to the memory system at a fixed time interval that corresponds to a worst case load transient event.
1. A method comprising:
providing an operation voltage to a memory system;
adjusting the operation voltage provided to the memory system during transient events of the memory system; and
adjusting the operation voltage provided to the memory system at a fixed time interval that corresponds to a worst case load transient event.
2. The method of claim 1 , wherein the adjusting of the operation voltage is in response to an initial time of a control signal input to the memory system, a period of the memory control signal, a maximum current demanded by the memory system, and a step current demanded by the memory system.
3. The method of claim 1 , wherein the adjusting of the operation voltage is to suppress transient noise in power delivery to the memory system.
4. The method of claim 1 , wherein the worst case load transient event corresponds to a memory refresh cycle.
5. The method of claim 1 , wherein the adjusting of the operation voltage is to control voltage transient noise within an acceptable range.
6. The method of claim 1 , wherein the adjusting of the operation voltage includes pulling up or pulling down the operational voltage during transient events of the memory system.
7. The method of claim 1 , further comprising providing an initial time and a period of a memory control signal, wherein the adjusting of the operation voltage is in response to the initial time and is in response to the period of the memory control signal.
8. The method of claim 1 , wherein the adjusting of the operation voltage is in response to an initial time and is in response to a period of a memory control signal.
9. The method of claim 1 , wherein the adjusting of the operation voltage is in response to a maximum current and a step current demanded by the memory system.
10. The method of claim 5 , wherein the adjusting of the operation voltage is in response to a maximum current and a step current demanded by the memory system.
11. The method of claim 1 , wherein the adjusting of the operation voltage is in response to a maximum current demanded by the memory system.
12. The method of claim 1 , wherein the adjusting of the operation voltage is in response to a step current demanded by the memory system.
13. The method of claim 5 , wherein the adjusting of the operation voltage is in response to a maximum current demanded by the memory system.
14. The method of claim 5 , wherein the adjusting of the operation voltage is in response to a step current demanded by the memory system.
15. The method of claim 1 , further comprising providing a maximum current and a step current demanded by the memory system, wherein the adjusting of the operation voltage is in response to the maximum current and the step current.
16. The method of claim 5 , further comprising providing a maximum current and a step current demanded by the memory system, wherein the adjusting of the operation voltage is in response to the maximum current and the step current.
17. The method of claim 1 , wherein the memory system includes a Dynamic Random Access Memory device.
18. The method of claim 1 , wherein the memory system includes at least one memory module.
19. The method of claim 1 , wherein the adjusting of the operation voltage is in response to one or more of an initial time of a control signal input to the memory system, a period of the memory control signal, a maximum current demanded by the memory system, and/or a step current demanded by the memory system.