High-linearity low noise amplifier and method

1. A low-noise amplifier (LNA) comprising:

a cascode amplifier;

a common-gate stage coupled to an output of the cascode amplifier; and

dynamic biasing circuitry to dynamically bias the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

2. A low-noise amplifier (LNA) comprising:

a cascode amplifier;

a common-gate stage coupled to an output of the cascode amplifier; and

dynamic biasing circuitry to dynamically bias the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the cascode amplifier comprises a common-source transistor coupled with a first common-gate transistor,

wherein the common-gate stage comprises a second common-gate transistor coupled to an output of the cascode amplifier, and

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

3. The LNA of claim 2 wherein a source of the first dynamic-biasing transistor is coupled with a drain of the second dynamic-biasing transistor,

wherein the source of the first dynamic-biasing transistor and the drain of the second dynamic-biasing transistor provide a dynamic gate bias voltage for the second common-gate transistor, and

wherein the dynamic gate bias voltage for the second common-gate transistor is offset by the offset voltage.

4. The LNA of claim 3 wherein the offset voltage is selected based on a source voltage of the first common-gate transistor.

5. The LNA of claim 3 wherein the dynamic biasing circuitry biases the second common-gate transistor to allow the first and second common-gate transistors to share approximately equal portions of the output voltage swing.

6. The LNA of claim 3 wherein the dynamic-biasing transistors comprise diode-configured transistors having their gates and drains coupled together, and

wherein the dynamic biasing circuitry further comprises a first resistive element and a second resistive element in series with the dynamic-biasing transistors.

7. The LNA of claim 6 wherein the first resistive element is coupled between the output voltage and a drain of the first dynamic-biasing transistor,

wherein the second resistive element is coupled between the offset voltage and a source of the second dynamic-biasing transistor, and

wherein the dynamic biasing circuitry further comprises:

a first capacitive element parallel with the first resistive element, and

a second capacitive element parallel with the second resistive element,

wherein the first and second capacitive elements provide high-frequency compensation.

8. The LNA of claim 3 wherein the common-source transistor, the first common-gate transistor, the second common-gate transistor, and the first and second dynamic-biasing transistors comprise N-MOS transistors.

9. The LNA of claim 1 wherein the LNA is a first single-ended LNA that is part of a differential LNA comprising the first single-ended LNA and a second single-ended LNA substantially identical to the first single-ended LNA,

wherein each single-ended LNA is to amplify each portion of a differential signal.

10. A method of amplifying comprising:

amplifying an RE input signal with a cascode amplifier and a common-gate stage coupled to an output of the cascode amplifier; and

dynamically biasing the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

11. A method of amplifying comprising:

amplifying an RE input signal with a cascode amplifier and a common-gate stage coupled to an output of the cascode amplifier; and

dynamically biasing the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the cascode amplifier comprises a common-source transistor coupled with a first common-gate transistor,

wherein the common-gate stage comprises a second common-gate transistor coupled to an output of the cascode amplifier, and

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

12. The method of claim 11 wherein a source of the first dynamic-biasing transistor is coupled with a drain of the second dynamic-biasing transistor,

wherein the method further comprises:

providing a dynamic gate bias voltage at a gate of the second common-gate transistor with the source of the first dynamic-biasing transistor and the drain of the second dynamic-biasing transistor; and

offsetting the dynamic gate bias voltage with the offset voltage.

13. The method of claim 12 wherein the dynamically biasing comprises dynamically biasing the second common-gate transistor to allow the first and second common-gate transistors to share approximately equal portions of the output voltage swing.

14. A receiver comprising a low-noise amplifier (LNA) to amplify an RF signal received through an antenna, wherein the LNA comprises a cascode amplifier, a common-gate stage coupled to an output of the cascode amplifier, and dynamic biasing circuitry to dynamically bias the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

15. A receiver comprising a low-noise amplifier (LNA) to amplify an RF signal received through an antenna, wherein the LNA comprises a cascode amplifier, a common-gate stage coupled to an output of the cascode amplifier, and dynamic biasing circuitry to dynamically bias the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage,

wherein the cascode amplifier comprises a common-source transistor coupled with a first common-gate transistor,

wherein the common-gate stage comprises a second common-gate transistor coupled to an output of the cascode amplifier, and

wherein the dynamic biasing circuitry comprises first and second dynamic-biasing transistors configured to form a voltage divider with an offset voltage.

16. The receiver of claim 15 wherein a source of the first dynamic-biasing transistor is coupled with a drain of the second dynamic-biasing transistor,

wherein the source of the first dynamic-biasing transistor and the drain of the second dynamic-biasing transistor provide a dynamic gate bias voltage for the second common-gate transistor, and

wherein the dynamic gate bias voltage for the second common-gate transistor is offset by the offset voltage.

17. The receiver of claim 16 wherein the offset voltage is selected based on a source voltage of the first common-gate transistor.

18. The receiver of claim 16 wherein the dynamic biasing circuitry biases the second common-gate transistor to allow the first and second common-gate transistors to share approximately equal portions of the output voltage swing.

19. The receiver of claim 16 wherein the dynamic-biasing transistors comprise diode-configured transistors having their gates and drains coupled together, and

wherein the dynamic biasing circuitry further comprises a first resistive element and a second resistive element in series with the dynamic-biasing transistors.

20. The receiver of claim 14 wherein the LNA is a differential LNA to amplify differential signals provided by an antenna,

wherein the differential LNA comprises two substantially identical single-ended LNAs, and

wherein each single-ended LNA comprises a cascode amplifier, a common-gate stage coupled to an output of the cascode amplifier, and dynamic biasing circuitry to dynamically bias the common-gate stage based on an output voltage of the common-gate stage to allow an output voltage swing to be shared between the cascode amplifier and the common-gate stage.