Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures

1. A memory structure, comprising:

a perpendicular magnetic tunnel junction (pMTJ) element disposed on a bottom electrode above a substrate;

a top electrode above the pMTJ element, the top electrode comprising a lateral strain-inducing material layer disposed on the pMTJ element, wherein the lateral strain-inducing material layer comprises a seam therein; and

an inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer, the ILD layer having an uppermost surface co-planar with an uppermost surface of the lateral strain-inducing material layer.

2. The memory structure of claim 1 , wherein the lateral strain-inducing material layer is a compressive lateral strain-inducing material layer.

3. The memory structure of claim 2 , wherein the compressive lateral strain-inducing material layer comprises a material selected from the group consisting of titanium and tungsten.

4. The memory structure of claim 1 , wherein the lateral strain-inducing material layer is a tensile lateral strain-inducing material layer.

5. The memory structure of claim 4 , wherein the tensile lateral strain-inducing material layer comprises a tantalum liner and copper fill material stack.

6. The memory structure of claim 1 , wherein the pMTJ element is disposed on a conductive pedestal.

7. The memory structure of claim 1 , wherein the ILD layer is also laterally adjacent to the conductive pedestal.

8. A semiconductor structure, comprising:

a plurality of metal 2 (M 2 ) line/via 1 (V 1 ) pairings disposed in a first dielectric layer disposed above a substrate;

a plurality of metal 3 (M 3 ) line/via 2 (V 2 ) pairings and a plurality of perpendicular magnetic tunnel junctions (pMTJs) disposed in a second dielectric layer disposed above the first dielectric layer, the plurality of M 3 /V 2 pairings coupled to a first portion of the plurality of M 2 /V 1 pairings, and the plurality of pMTJs coupled to a second portion of the plurality of M 2 /V 1 pairings, wherein each of the plurality of pMTJs has a top electrode comprising a lateral strain-inducing material layer on a MTJ material stack, wherein the lateral strain-inducing material layer comprises a seam therein; and

a plurality of metal 4 (M 4 ) line/via 3 (V 3 ) pairings and a plurality of metal 4 (M 4 ) line/via to junction (VTJ) pairings disposed in a third dielectric layer disposed above the second dielectric layer, the plurality of M 4 /V 3 pairings coupled to the plurality of M 3 /V 2 pairings, and the plurality of M 4 /VTJ pairings coupled to the plurality of pMTJs.

9. The semiconductor structure of claim 8 , wherein the lateral strain-inducing material layer is a compressive lateral strain-inducing material layer.

10. The semiconductor structure of claim 8 , wherein the lateral strain-inducing material layer is a tensile lateral strain-inducing material layer.

11. The semiconductor structure of claim 8 , wherein each of the plurality of pMTJs is disposed on a corresponding one of a plurality of conductive pedestals disposed in the second dielectric layer.

12. The semiconductor structure of claim 11 , wherein each of the plurality of conductive pedestals comprises a material selected from the group consisting of titanium nitride, tantalum nitride, tantalum, ruthenium and cobalt.

13. The semiconductor structure of claim 11 , wherein each of the plurality of conductive pedestals is wider than the corresponding one of the plurality of pMTJs disposed thereon.

14. The semiconductor structure of claim 13 , further comprising:

a dielectric spacer layer disposed along sidewalls of each of the plurality of pMTJs.

15. The semiconductor structure of claim 14 , wherein the dielectric spacer layer extends onto exposed top surfaces of each of the plurality of conductive pedestals.