Fine granularity DRAM refresh
View Patent ↗A method, device, and system are included. In one embodiment, the method included issuing a single row refresh command for a first row in a memory starting at a target address, incrementing a row counter, continuing issuing a single row refresh command for each subsequent row in the memory and incrementing the row counter until the number of row counter increments is equal to the number of rows of the memory refreshed as a result of a refresh (REF) command.
1. A method, comprising:
issuing a single row refresh command for a first row in a memory starting at a target address;
incrementing a row counter;
continuing to issue a single row refresh command for each subsequent row in the memory and incrementing the row counter until the number of row counter increments is equal to the number of rows of the memory refreshed as a result of a refresh (REF) command.
2. The method of claim 1 , further comprising allowing one or more memory access requests to access the memory after each single row refresh command.
3. The method of claim 2 , wherein memory access requests include memory read commands and memory write commands.
4. The method of claim 1 , wherein a single row refresh command further comprises a single row activate (ACT_R) command followed by a precharge (PRE) command.
5. The method of claim 1 , further comprising resetting the row counter to zero after every row of memory targeted by the REF command has been issued a single row refresh command.
6. The method of claim 5 , further comprising incrementing a REF counter each time the row counter resets.
7. The method of claim 1 , further comprising dynamically changing between using a REF command for memory refresh cycles and issuing a single row refresh for memory refresh cycles.
8. The method of claim 7 , further comprising:
issuing single row memory refreshes when a temperature within a computer system is at or above a threshold temperature; and
issuing REF command memory refreshes when the temperature within the computer system is below the threshold temperature.
9. The method of claim 7 , further comprising:
issuing single row memory refreshes when the data throughput of a memory bus is greater than or equal to a threshold bandwidth; and
issuing REF command memory refreshes when the data throughput of a memory bus is less than a threshold bandwidth.
10. A memory controller device, comprising circuitry to:
issue a single row refresh command for a first row in a memory starting at a target address;
increment a row counter;
continue to issue a single row refresh command for each subsequent row in the memory and to increment the row counter until the number of row counter increments is equal to the number of rows of the memory refreshed as a result of a refresh (REF) command.
11. The memory controller device of claim 10 , further comprising circuitry to allow one or more memory access requests to access the memory after each single row refresh command.
12. The memory controller device of claim 11 , wherein memory access requests include memory read commands and memory write commands.
13. The memory controller device of claim 10 , wherein a single row refresh command further comprises a single row activate (ACT_R) command followed by a precharge (PRE) command.
14. The memory controller device of claim 10 , further comprising circuitry to reset the row counter to zero after every row of memory targeted by the REF command has been issued a single row refresh command.
15. The memory controller device of claim 14 , further comprising circuitry to increment a REF counter each time the row counter resets.
16. The memory controller device of claim 10 , further comprising circuitry to determine the number of rows of the memory that are refreshed as a result of the REF command when the device is powered on.
17. A system, comprising:
a bus;
a processor coupled to the bus;
a memory coupled to the bus;
a network interface card coupled to the bus; and
a memory controller device coupled to the bus, the memory controller device comprising circuitry to:
issue a single row refresh command for a first row in a memory starting at a target address;
increment a row counter;
continue to issue a single row refresh command for each subsequent row in the memory and to increment the row counter until the number of row counter increments is equal to the number of rows of the memory refreshed as a result of the a refresh (REF) command.
18. The system of claim 17 , wherein the memory controller device allows one or more memory access requests to access the memory after each single row refresh command.
19. The system of claim 18 , wherein memory access requests include memory read commands and memory write commands.
20. The system of claim 17 , wherein a single row refresh command further comprises a single row activate (ACT_R) command followed by a precharge (PRE) command.
21. The system of claim 17 , wherein the memory controller device resets the row counter to zero after every row of memory targeted by the REF command has been issued a single row refresh command.
22. The system of claim 21 , wherein the memory controller device increments a REF counter each time the row counter resets.
23. The system of claim 17 , wherein the memory comprises dynamic random access memory (DRAM).