Forming a non-planar transistor having a quantum well channel
View Patent ↗In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
1. An apparatus comprising:
a substrate;
a buried oxide layer directly formed on the substrate;
a silicon on insulator (SOI) core formed directly on the buried oxide layer, the SOI core formed of a silicon fin on the buried oxide layer;
a quantum well (QW) layer wrapped directly around the SOI core, wherein the QW layer is compressive strained and is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%; and
a silicon layer wrapped around the QW layer, wherein the silicon layer is tensile strained, and wherein the simultaneous introduction of the compressive strain and the tensile strain is to optimize transport of electrons and holes.
2. The apparatus of claim 1 , further comprising:
a gate dielectric layer formed over the silicon layer; and
a gate electrode layer formed over the gate dielectric layer.
3. The apparatus of claim 2 , wherein the apparatus comprises a non-planar transistor, wherein the quantum well layer comprises a channel of the non-planar transistor.
4. The apparatus of claim 3 , wherein the non-planar transistor comprises a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT).
5. The apparatus of claim 1 , wherein the silicon layer has a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
6. An apparatus comprising:
a high electron mobility transistor (HEMT) including:
a substrate;
a buried oxide layer directly formed on the substrate;
a silicon on insulator (SOI) core formed directly on the buried oxide layer, the SOI core formed of a silicon fin on the buried oxide layer;
a quantum well (QW) layer wrapped directly around the SOI core, wherein the QW layer is compressive strained and is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%; and
a silicon layer wrapped around the QW layer, wherein the silicon layer has a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
7. The apparatus of claim 6 , further comprising:
a gate dielectric layer formed over the silicon layer; and
a gate electrode layer formed over the gate dielectric layer.
8. The apparatus of claim 7 , wherein the simultaneous introduction of the compressive strain and the tensile strain is to optimize transport of electrons and holes.
9. An apparatus comprising:
a high hole mobility transistor (HHMT) including:
a substrate;
a buried oxide layer directly formed on the substrate;
a silicon on insulator (SOI) core formed directly on the buried oxide layer, the SOI core formed of a silicon fin on the buried oxide layer;
a quantum well (QW) layer wrapped directly around the SOI core, wherein the QW layer is compressive strained and is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%; and
a silicon layer wrapped around the QW layer, wherein the silicon layer has a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
10. The apparatus of claim 9 , further comprising:
a gate dielectric layer formed over the silicon layer; and
a gate electrode layer formed over the gate dielectric layer.
11. The apparatus of claim 10 , wherein the simultaneous introduction of the compressive strain and the tensile strain is to optimize transport of electrons and holes.