PCI express tunneling over a multi-protocol I/O interconnect
View Patent ↗Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
1. An input/output (I/O) interconnect apparatus comprising:
a switch fabric, the switch fabric comprising a plurality of ports, including a first port, a second port, and a third port;
wherein the first port is to communicatively couple a first controller to the I/O interconnect, to implement a first layer of a first protocol, and to encapsulate packets of the first protocol into packets of the I/O interconnect;
wherein the second port is to communicatively couple a second controller to the I/O interconnect, to implement a first layer of a second protocol, and to encapsulate packets of the second protocol into packets of the I/O interconnect; and
wherein the third port is to communicatively couple a peripheral device to the I/O interconnect,
wherein packets of the I/O interconnect comprise a packet header, the packet header comprising a protocol defined field to maintain synchronization between the first port and a corresponding port of the peripheral device.
2. The apparatus of claim 1 , wherein the packet header further comprises a hop id field to provide an identifier associated with a corresponding path between two of the plurality of ports of the switch fabric.
3. The apparatus of claim 2 , wherein the packet header further comprises a length field to indicate a number of bytes in a payload of a corresponding packet of the I/O interconnect.
4. The apparatus of claim 3 , wherein the packet header further comprises a header error correction control field to enable single-bit error correction for a corresponding packet of the I/O interconnect.
5. The apparatus of claim 1 , wherein the first protocol is a peripheral component interconnect express (PCIe) protocol.
6. An input/output (I/O) interconnect apparatus comprising:
a switch fabric, the switch fabric comprising a plurality of ports, including a first port, a second port, and a third port;
wherein the first port is to communicatively couple a first controller to the I/O interconnect, to implement a first layer of a first protocol, and to encapsulate packets of the first protocol into packets of the I/O interconnect;
wherein the second port is to communicatively couple a second controller to the I/O interconnect, to implement a first layer of a second protocol, and to encapsulate packets of the second protocol into packets of the I/O interconnect; and
wherein the third port is to communicatively couple a peripheral device to the I/O interconnect, wherein the switch fabric further comprises a time management unit to enable distribution and synchronization of time in the switch fabric.
7. An input/output (I/O) interconnect apparatus comprising:
a switch fabric, the switch fabric comprising a plurality of ports, including a first port, a second port, and a third port;
wherein the first port is to communicatively couple a first controller to the I/O interconnect, to implement a first layer of a first protocol, and to encapsulate packets of the first protocol into packets of the I/O interconnect;
wherein the second port is to communicatively couple a second controller to the I/O interconnect, to implement a first layer of a second protocol, and to encapsulate packets of the second protocol into packets of the I/O interconnect; and
wherein the third port is to communicatively couple a peripheral device to the I/O interconnect, wherein the switch fabric comprises a plurality of cross-bar switches.