No-touch stress testing of memory I/O interfaces
View Patent ↗Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
1. An apparatus comprising:
a system element to be coupled with a dynamic random-access memory (DRAM), the system element including:
a memory input/output (I/O) interface for connection with the DRAM, the interface including a driver and a receiver,
a memory controller for control of the DRAM, and
a timing stress testing logic for testing of the memory I/O interface, wherein the timing stress logic provides for characteristic testing to establish threshold levels for the memory I/O interface and failure testing to determine if a memory I/O interface meets threshold level requirements.
2. The apparatus of claim 1 , wherein the timing stress testing logic includes:
a multiplexer to choose between a functional path and a test path,
a pattern generator to generate a test pattern,
one or more digital delay locked loops (DLLs) to provide delays in the test path,
an auto-timing component, the auto-timing component to increment the one or more DLLs through delay values for the characteristic testing of the memory I/O interface and to set the one or more DLLs at threshold levels for the failure test of the memory I/O interface, and
an I/O pattern comparator to compare resulting signals from the memory I/O interface to the test pattern to determine passing or failing of the memory I/O interface.
3. The apparatus of claim 2 , wherein the one or more DLLs include a first DLL coupled with the driver and a second DLL coupled with the receiver.
4. The apparatus of claim 3 , further comprising a first finite state machine to set a delay of the first DLL and a second finite state machine to set a delay of the second DLL.
5. The apparatus of claim 4 , wherein the auto-timing component is to control operation of the first finite state machine and the second finite state machine for the characteristic testing of the memory I/O interface and for the failure testing of the memory I/O interface.
6. The apparatus of claim 5 , wherein the auto-timing component is operable to increment the first finite state machine and the second finite state machine through a plurality of increasing delay values for the characterization test of the memory device.
7. The apparatus of claim 5 , wherein the auto-timing component is operable to set the first finite state machine and the second finite state machine at the threshold levels for the failure test of the memory I/O interface.
8. The apparatus of claim 2 , wherein the driver and receiver are coupled in the memory I/O interface with a micro-bump connection.
9. The apparatus of claim 8 , wherein the system element includes a plurality of through silicon vias (TSVs), including a first TSV coupled with the micro-bump.
10. The apparatus of claim 1 , wherein the memory controller and timing stress testing logic are separate elements of the system element.
11. The apparatus of claim 1 , wherein the timing stress testing logic is a portion of the system element.
12. The apparatus of claim 1 , wherein the system element is a system on chip (SoC).
13. The apparatus of claim 1 , further comprising a memory stack coupled with the system element, the memory stack including one or more DRAM layers.
14. A method comprising:
selecting a test process for a memory I/O interface, wherein the test process is one of a characteristic test to establish threshold levels for the memory I/O interface or a failure test for a unit including the memory I/O interface to determine if the unit meets threshold level requirements;
commencing the selected test process for the memory I/O interface;
generating a test pattern for the memory I/O interface;
switching a signal path to an I/O interface test path, wherein the signal path may be switched to either the I/O interface test path or a functional path;
setting one or more delays for the signal path;
applying the test pattern to the memory I/O interface and detecting an output from the memory I/O interface;
comparing the output from the memory I/O interface with the test pattern;
for characteristic testing, establishing threshold levels based on the comparison of the output from the memory I/O interface with the test pattern; and
for failure testing, determining whether the unit including the memory I/O interface meets threshold level requirements based on the comparison of the output of the memory I/O interface with the test pattern.
15. The method of claim 14 , wherein the characteristic testing of the memory I/O interface and the failure testing of the memory I/O interface utilize a same timing stress logic.
16. The method of claim 15 , wherein, for the characteristic testing of the memory I/O interface, setting the one or more delays includes setting the one or more delays at an initial setting.
17. The method of claim 15 , wherein the characteristic testing of the memory I/O interface further includes incrementing the one or more delays for a subsequent comparison if the comparison between the output and the test pattern does not indicate a failure.
18. The method of claim 15 , wherein, for the failure testing of the unit including memory I/O interface, setting the one or more delays for the signal path includes setting the delays at a failure threshold setting.
19. The method of claim 18 , wherein the failure threshold setting is established by a characterization test of the memory I/O interface.
20. The method of claim 14 , wherein the test process occurs without attachment of memory to the memory I/O interface.
21. A system comprising:
a processor to process data for the system;
a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both; and
a combined memory device including a system on chip (SoC) and a memory stack including one or more DRAM layers, the memory stack being coupled to SoC by a micro-bump connection, the system element includes a plurality of through silicon vias (TSVs), including a first TSV coupled with a first micro-bump;
wherein the SoC includes:
a memory input/output (I/O) interface, the interface including a driver and a receiver,
a memory controller for control of the DRAM, and
a timing stress testing logic for testing of the memory I/O interface, wherein the timing stress logic provides for characteristic testing to establish threshold levels for the memory I/O interface and failure testing to determine if a memory I/O interface meets threshold level requirements.
22. The system of claim 21 , wherein the timing stress testing logic including:
a multiplexer to choose between a functional path and a test path,
a pattern generator to generate a test pattern,
one or more digital delay locked loops (DLLs) to provide delays in the test path,
an auto-timing component, the auto-timing component to increment the one or more DLLs through delay values for the characteristic testing of the memory I/O interface and to set the one or more DLLs at threshold levels for the failure test of the memory I/O interface, and
an I/O pattern comparator to compare resulting signals from the memory I/O interface to the test pattern to determine passing or failing of the memory I/O interface.
23. The system of claim 22 , wherein the one or more DLLs include a first DLL coupled with the driver and a second DLL coupled with the receiver.
24. The system of claim 23 , further comprising a first finite state machine to set a delay of the first DLL and a second finite state machine to set a delay of the second DLL.
25. The system of claim 24 , wherein the auto-timing component to control operation of the first finite state machine and the second finite state machine for the characteristic testing of the memory I/O interface and for the failure testing of the memory I/O interface.
26. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
selecting a test process for a memory I/O interface, wherein the test process is one of a characteristic test to establish threshold levels for the memory I/O interface or a failure test for a unit including the memory I/O interface to determine if the unit meets threshold level requirements;
commencing a test process for a memory I/O interface, wherein the test process is one of a characteristic test to establish threshold levels for the memory I/O interface or a failure test for a unit including the memory I/O interface to determine if the unit meets threshold level requirements;
commencing the selected test process for the memory I/O interface;
switching a signal path to an I/O interface test path, wherein the signal path may be switched to either the I/O interface test path or a functional path;
setting one or more delays for the signal path;
applying the test pattern to the memory I/O interface and detecting an output from the memory I/O interface;
comparing the output from the memory I/O interface with the test pattern;
for characteristic testing, establishing threshold levels based on the comparison of the output from the memory I/O interface with the test pattern; and
for failure testing, determining whether the unit including the memory I/O interface meets threshold level requirements based on the comparison of the output of the memory I/O interface with the test pattern.