IP Library Granted Patent US 10,275,260
Granted Patent B2
US 10,275,260 · App. 15/262,816 · Granted Apr 30, 2019

Collaborative processor and system performance and power management

Inventors: Guy M. Therien (Beaverton, OR); Paul S. Diefenbaugh (Portland, OR); Anil Aggarwal (Portland, OR); Andrew D. Henroid (Portland, OR); Jeremy J. Shrall (Portland, OR); Efraim Rotem (Haifa, IL); Krishnakanth V. Sistla (Beaverton, OR); Eliezer Weissmann (Haifa, IL)
Assignee: Intel Corporation
G06F9/4403G06F1/26G06F1/28G06F1/3203G06F1/324G06F1/3234G06F1/3275G06F1/3296G06F9/22G06F9/44G06F9/4401G06F9/445G06F9/4418G06F11/3024G06F11/3409G06F11/3664G06F11/3672G06F11/3688G06F17/30339G06F1/206G06F1/32G06F9/3012G06F9/30098G06F9/384G06F11/3447G06F11/3466G06F15/7871G06F2209/501G06F2217/78Y02D10/126Y02D10/172
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Quick Facts
Patent No.
US 10,275,260
App. No.
15/262,816
Granted
Apr 30, 2019
Kind
B2
Abstract

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Claims (39)

1. An apparatus for flexible power management, the apparatus comprising:

one or more platform power management interface registers including:

one or more capabilities registers;

one or more control registers; and

one or more feedback registers;

logic to read the one or more platform power management interface registers; and

a power control unit (PCU) residing in a processor, wherein the PCU is communicatively coupled to the one or more platform power management interface registers, and wherein the PCU is to provide a requested performance according to the read one or more platform power management interface registers.

2. The apparatus of claim 1 , wherein the one or more capabilities registers indicate performance scale parameters, capabilities or thresholds.

3. The apparatus of claim 1 , wherein the one or more control registers indicate requested performance from the processor.

4. The apparatus of claim 1 , wherein the one or more feedback registers indicate delivered performance parameters.

5. The apparatus of claim 4 , wherein the delivered performance parameters are estimated, measured, or monitored performance parameters.

6. The apparatus of claim 1 , wherein the one or more platform power management interface registers are accessible by an operating system directed configuration and power management (OSPM).

7. The apparatus of claim 1 comprises logic to select a plurality of performance values, wherein a platform is inhibited from varying a performance above or below a selected performance level when selected.

8. The apparatus of claim 7 comprises logic to evaluate platform performance for the plurality of selected performance values, wherein an OS is to select values in the performance value range from a Lowest through a Nominal value, while running a characterization workload.

9. The apparatus of claim 7 , wherein the platform is inhibited by selecting performance value parameters that set a minimum, maximum, and desired performance value to the same value.

10. A system for flexible power management, the system comprising:

a hardware platform interface for communicating with an operating system (OS);

one or more platform power management interface registers including:

one or more capabilities registers;

one or more control registers; and

one or more feedback registers;

wherein the OS is to read the one or more platform power management interface registers; and

a processor communicatively coupled to the hardware platform interface, wherein the processor includes:

a mode specific register (MSR) interface to control performance and power consumption, wherein the MSR interface is to communicate with a baseboard management controller on a server platform; and

a power control unit (PCU) to provide a requested performance according to the read one or more platform power management interface registers.

11. The system of claim 10 , wherein:

the one or more capabilities registers indicate performance scale parameters, capabilities or thresholds;

the one or more control registers indicate requested performance from a platform processor; and

the one or more feedback registers indicate delivered performance parameters.

12. The system of claim 10 , wherein the OS is to select a plurality of performance values, wherein a platform is inhibited from varying a performance above or below a selected performance level when selected.

13. The system of claim 12 , wherein the OS is to evaluate platform performance for the plurality of selected performance values, wherein the OS is to select values in the performance value range from a Lowest through a Nominal value, while running a characterization workload.

14. The system of claim 13 , wherein the platform is inhibited by selecting performance value parameters that set a minimum, maximum, and desired performance value to the same value.

15. One or more machine-readable storage media having machine executable instructions stored there on, that when executed, cause one or more processors to perform an operation comprising:

read one or more platform power management interface registers to determine a range of available performance values;

select a plurality of performance values, wherein a platform is inhibited from varying a delivered performance above or below a selected performance level when selected; and

evaluate platform performance for the plurality of selected performance values, wherein values are selected in the performance value range from a Lowest through a Nominal value, while running a characterization workload.

16. The one or more machine-readable storage media of claim 15 , wherein inhibiting includes selecting performance value parameters that set a minimum, maximum, and desired performance value to the same value.

17. The one or more machine-readable storage media of claim 15 , wherein different characterization workloads are used to evaluate performance levels for different processing task types.

18. The one or more machine-readable storage media of claim 17 , wherein at least one of the processing task types includes a quality of service (QoS) task type to determine minimum performance levels desired for one or more different QoS scenarios.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (3)
Continuation 13976507
Provisional Application 61563030 · Nov 22, 2011
Related Publication 20170003724A1 · Jan 5, 2017