Metal gate transistors with raised source and drain regions formed on heavily doped substrate
View Patent ↗An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor.
1. A PMOS transistor comprising:
a monocrystalline silicon substrate comprising a heavily doped upper region;
an un-doped or lightly doped monocrystalline silicon channel region disposed directly on an uppermost surface of the monocrystalline silicon substrate and having a top surface;
a pair of source and drain regions, each source and drain region comprising an epitaxial silicon germanium first portion disposed directly on the uppermost surface of the monocrystalline silicon substrate, directly adjacent to the un-doped or lightly doped monocrystalline silicon channel region and extending upwards directly from the uppermost surface of the monocrystalline silicon substrate to above the top surface of the un-doped or lightly doped monocrystalline silicon channel region, and each source and drain region further comprising a second portion extending only partially into the monocrystalline silicon substrate, the second portion directly below the first portion; and
a metal gate insulated from and disposed above and over the un-doped or lightly doped monocrystalline silicon channel region, and above and over at least a part of the first portion of each of the source and drain regions, wherein the first portion of each of the source and drain regions comprises an angled faceted profile between the epitaxial silicon germanium and the un-doped or lightly doped monocrystalline silicon channel region underneath the metal gate, and wherein the second portion of each of the source and drain regions comprises only one rounded diffusion corner profile, the one rounded diffusion corner profile below, but not underneath, the metal gate.
2. The transistor of claim 1 , further including first sidewall spacers disposed about the metal gate.
3. The transistor of claim 2 , further including a silicide layer on at least a part of the first portion of each of the source and drain regions.
4. The transistor of claim 1 , wherein the heavily doped upper region of the monocrystalline silicon substrate has a peak doping concentration of 10 19 atoms/cm 3 or greater.
5. A PMOS transistor comprising:
a monocrystalline silicon substrate comprising a heavily doped upper region;
an un-doped or lightly doped monocrystalline silicon channel region disposed directly on an uppermost surface of the monocrystalline silicon substrate and having a top surface;
a pair of source and drain regions, each source and drain region comprising an epitaxial silicon germanium first portion disposed directly on the uppermost surface of the monocrystalline silicon substrate, directly adjacent to the un-doped or lightly doped monocrystalline silicon channel region and extending upwards directly from the uppermost surface of the monocrystalline silicon substrate to above the top surface of the un-doped or lightly doped monocrystalline silicon channel region, and each source and drain region further comprising a second portion extending only partially into the monocrystalline silicon substrate, the second portion directly below the first portion; and
a non-silicon metal gate insulated from and disposed over the un-doped or lightly doped monocrystalline silicon channel region, and over at least a part of the first portion of each of the source and drain regions, wherein the first portion of each of the source and drain regions comprises an angled faceted profile between the epitaxial silicon germanium and the un-doped or lightly doped monocrystalline silicon channel region underneath the non-silicon metal gate, and wherein the second portion of each of the source and drain regions comprises only one rounded diffusion corner profile, the one rounded diffusion corner profile below, but not underneath, the non-silicon metal gate.
6. The transistor of claim 5 , further including first sidewall spacers disposed about the metal gate.
7. The transistor of claim 6 , further including a silicide layer on at least a part of the first portion of each of the source and drain regions.
8. The transistor of claim 5 , wherein the heavily doped upper region of the monocrystalline substrate has a peak doping concentration of 10 19 atoms/cm 3 or greater.