Multi-core shared page miss handler
Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.
1. An apparatus comprising:
a plurality of requesting devices to concurrently access a paged virtual memory space, said plurality of requesting devices including a plurality of processing cores respectively having cache memories;
a page miss request queue to receive and enqueue at least two page miss requests for respective misses in translation lookaside buffers (TLBs) of each of at least two of the plurality of requesting devices;
arbitration logic to identify a first page miss request of the at least two enqueued page miss requests to process;
a single, shared page miss handler (PMH) to perform a page table walk to generate a physical address responsive to the first page miss request;
PMH duplication logic to eliminate a duplicate page table walk and a duplicate page fault among the at least two enqueued page miss requests; and
communication logic to, when the page table walk does not result in a fault, send the physical address to an operating system for a corresponding requesting device, and, otherwise, when the page table walk does result in a fault, send a signal fault to the operating system for the corresponding requesting device responsive to the first page miss request.
2. The apparatus of claim 1 , further comprising logic to signal a fault for the corresponding requesting device responsive to the first page miss request.
3. The apparatus of claim 1 , further comprising a TLB coupled with the PMH to store the physical address after the page table walk.
4. The apparatus of claim 1 , wherein the plurality of requesting devices comprises a graphics processor.
5. The apparatus of claim 1 , wherein the plurality of requesting devices comprises a transport processor.
6. The apparatus of claim 1 , wherein the plurality of requesting devices comprises a security processor.
7. The apparatus of claim 1 , wherein the plurality of requesting devices comprises a video device.
8. A method comprising:
receiving and enqueuing, at a shared page miss handler (PMH), at least two page miss requests in a page miss request queue for at least two respective misses in translation lookaside buffers (TLBs) of each of at least two of the plurality of requesting devices, each requesting device to concurrently access a paged virtual memory space, said plurality of requesting devices including a plurality of processing cores respectively having cache memories;
identifying a first page miss request of a plurality of enqueued page miss requests to process;
eliminating, using PMH duplication logic, a duplicate page table walk and a duplicate page fault from among the enqueued page miss requests;
performing a page table walk with a single, shared page miss handler (PMH) to generate a physical address responsive to the first page miss request; and
when the page table walk does not result in a fault, sending the physical address to an operating system for a corresponding requesting device, otherwise, when the page table walk does result in a fault, signal a fault to the operating system for the corresponding requesting device responsive to the first page miss request.
9. The method of claim 8 , further comprising signaling a fault for the corresponding requesting device responsive to the first page miss request.
10. The method of claim 8 , further comprising storing the physical address after the page table walk in a TLB coupled with the PMH.
11. The method of claim 8 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a graphics processor of the plurality of requesting devices.
12. The method of claim 8 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a transport processor of the plurality of requesting devices.
13. The method of claim 8 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a security processor of the plurality of requesting devices.
14. The method of claim 8 , wherein the receiving comprises receiving a page miss request in the page miss request queue for a respective miss in a translation lookaside buffer (TLB) of a video device of the plurality of requesting devices.