Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
View Patent ↗Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
1. A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and
a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising:
a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of the channel region; and
a gate electrode disposed on the second dielectric layer.
2. The semiconductor device of claim 1 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
3. The semiconductor device of claim 2 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
4. The semiconductor device of claim 2 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ).
5. The semiconductor structure of claim 1 , wherein the first dielectric layer has a thickness approximately in the range of 2-15 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
6. The semiconductor structure of claim 1 , the hetero-structure further comprising:
a top barrier layer disposed between the source and drain material region and the three-dimensional group III-V material body, wherein the trench is also disposed in the top barrier layer.
7. A semiconductor device, comprising:
a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate;
a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising:
a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and
a gate electrode disposed on the second dielectric layer;
a bottom barrier layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the bottom barrier layer; and
source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack.
8. The semiconductor structure of claim 7 , further comprising:
a top barrier layer disposed between the source and drain regions and each of the group III-V material nanowires.
9. The semiconductor device of claim 7 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
10. The semiconductor device of claim 9 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
11. The semiconductor device of claim 9 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ).
12. The semiconductor structure of claim 7 , wherein the first dielectric layer has a thickness approximately in the range of 2-15 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
13. A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region, and further comprising a bottom barrier layer disposed between the substrate and the three-dimensional group III-V material body;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, the trench also partially disposed in the bottom barrier layer and completely exposing the channel region; and
a gate stack disposed in the trench and on and completely surrounding the channel region, the gate stack comprising:
a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region;
a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region; and
a gate electrode disposed on the second dielectric layer.
14. The semiconductor device of claim 13 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
15. The semiconductor device of claim 14 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
16. The semiconductor device of claim 14 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ).
17. The semiconductor structure of claim 13 , wherein the first dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
18. The semiconductor structure of claim 13 , the hetero-structure further comprising:
a top barrier layer disposed between the source and drain material region and the three-dimensional group III-V material body, wherein the trench is also disposed in the top barrier layer.
19. A semiconductor device, comprising:
a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate;
a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising:
a first dielectric layer disposed on each of the channel regions;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the first dielectric layer, but not on each of the channel regions; and
a gate electrode disposed on the second dielectric layer; and
source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack.
20. The semiconductor structure of claim 19 , further comprising:
a top barrier layer disposed between the source and drain regions and each of the group III-V material nanowires.
21. The semiconductor structure of claim 19 , further comprising:
a bottom barrier layer disposed between the substrate and the bottom-most group III-V material nanowire, wherein a bottom portion of the gate stack is disposed on the bottom barrier layer.
22. The semiconductor device of claim 19 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
23. The semiconductor device of claim 22 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
24. The semiconductor device of claim 22 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ).
25. The semiconductor structure of claim 19 , wherein the first dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
26. A semiconductor device, comprising:
a vertical arrangement of a plurality of group III-V material nanowires disposed above a substrate;
a gate stack disposed on and completely surrounding channel regions of each of the group III-V material nanowires, the gate stack comprising:
a first dielectric layer disposed on outer portions, but not an inner portion, of each of the channel regions;
a second, different, dielectric layer conformal with the first dielectric layer and disposed on the inner portion of each of the channel regions; and
a gate electrode disposed on the second dielectric layer;
source and drain regions disposed in or on each of the group III-V material nanowires, on either side of the gate stack; and
a top barrier layer disposed between the source and drain regions and each of the group III-V material nanowires.
27. The semiconductor device of claim 26 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
28. A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region; and
a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising:
a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region;
a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region, wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8; and
a gate electrode disposed on the second dielectric layer.
29. The semiconductor structure of claim 28 , wherein the first dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
30. A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional group III-V material body with a channel region;
a source and drain material region disposed above the three-dimensional group III-V material body;
a trench disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region; and
a gate stack disposed in the trench and on the exposed portion of the channel region, the gate stack comprising:
a first dielectric layer conformal with the trench and disposed on the exposed portion of the channel region;
a second, different, dielectric layer conformal with and disposed on the first dielectric layer, but not on the channel region, wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer, and wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ); and
a gate electrode disposed on the second dielectric layer.
31. The semiconductor structure of claim 30 , wherein the first dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.