Methods and apparatus for improving impedance tolerance of on-die termination elements
View Patent ↗An impedance calibration circuit in an integrated circuit includes a master current source to force a master current to flow through a first load that is external to the integrated circuit. The master current source includes a stabilized current source to provide a first part of the master current and a first supplementary current source to provide a supplementary part of the master current.
1. An integrated circuit comprising an impedance calibration circuit, wherein said impedance calibration circuit comprises:
a master current source to force a master current to flow through a first load that is external to said integrated circuit, said master current source comprising:
a stabilized current source to provide a first part of said master current and to generate an indication of said first part of said master current; and
a first supplementary current source to provide a supplementary part of said master current; and
a slave current source to force a slave current to flow through a second load, said slave current source comprising:
a controlled current source to receive said indication and to provide a first part of said slave current; and
a second supplementary current source to provide a supplementary part of said slave current.
2. The integrated circuit of claim 1 , wherein said supplementary part of said master current is limited.
3. The integrated circuit of claim 1 , wherein said first supplementary current source is switchable.
4. The integrated circuit of claim 1 , wherein said master current source is differential.
5. The integrated circuit of claim 1 , wherein said master current source is differential and said first supplementary current source comprises one or more resistive elements to provide said supplementary part of said master current to said first load.
6. The integrated circuit of claim 5 , wherein said first supplementary current source further comprises a resistive voltage divider coupled in parallel with said first load, wherein said one or more resistive elements are transistors, and wherein gates of said one or more resistive elements are coupled to said resistive voltage divider.
7. The integrated circuit of claim 1 , wherein said second supplementary current source is substantially identical to said first supplementary current source.
8. The integrated circuit of claim 1 , wherein said second load has a controllable impedance, and wherein said impedance calibration circuit further comprises:
a measurement circuit to provide an indication of the difference between a first voltage drop across said first load and a second voltage drop across said second load; and
an impedance adjustment circuit to receive said indication of the difference in voltage drop and to adjust said controllable impedance in order to minimize the difference between said first voltage drop and said second voltage drop.
9. The integrated circuit of claim 8 , further comprising a low voltage differential signaling receiver and a termination element connected between a positive input terminal of said receiver and a negative input terminal of said receiver, wherein said termination element has a controllable impedance, and wherein said impedance adjustment circuit is to adjust said controllable impedance of said termination element in conjunction with adjusting said controllable impedance of said second load.
10. The integrated circuit of claim 8 , further comprising a low voltage differential signaling driver and a termination element connected between a positive output terminal of said driver and a negative output terminal of said driver, wherein said termination element has a controllable impedance, and wherein said impedance adjustment circuit is to adjust said controllable impedance of said termination element in conjunction with adjusting said controllable impedance of said second load.
11. The integrated circuit of claim 1 , wherein said integrated circuit is a processor.
12. An apparatus comprising:
a communication medium;
a first load; and
an integrated circuit coupled to said communication medium and comprising an impedance calibration circuit, wherein said impedance calibration circuit comprises:
a master current source to force a master current to flow through said first load, said master current source comprising:
a stabilized current source to provide a first part of said master current and to generate an indication of said first part of said master current; and
a first supplementary current source to provide a supplementary part of said master current; and
a slave current source to force a slave current to flow through a second load, said slave current source comprising:
a controlled current source to receive said indication and to provide a first part of said slave current; and
a second supplementary current source to provide a supplementary part of said slave current.
13. The apparatus of claim 12 , wherein said supplementary part of said master current is limited.
14. The apparatus of claim 12 , wherein said first supplementary current source is switchable.
15. The apparatus of claim 12 , wherein said master current source is differential.
16. The apparatus of claim 12 , wherein said master current source is differential and said first supplementary current source comprises one or more resistive elements to provide said supplementary part of said master current to said first load.
17. The apparatus of claim 16 , wherein said first supplementary current source further comprises a resistive voltage divider coupled in parallel with said first load, wherein said one or more resistive elements are transistors, and wherein gates of said one or more resistive elements are coupled to said resistive voltage divider.
18. The apparatus of claim 12 , wherein said second supplementary current source is substantially identical to said first supplementary current source.
19. The apparatus of claim 12 , wherein said second load has a controllable impedance, and wherein said impedance calibration circuit further comprises:
a measurement circuit to provide an indication of the difference between a first voltage drop across said first load and a second voltage drop across said second load; and
an impedance adjustment circuit to receive said indication of the difference in voltage drop and to adjust said controllable impedance in order to minimize the difference between said first voltage drop and said second voltage drop.
20. The apparatus of claim 19 , further comprising a communication medium, wherein said integrated circuit further comprises:
a low voltage differential signaling receiver and a termination element connected between a positive input terminal of said receiver and a negative input terminal of said receiver, said termination element having a controllable impedance, wherein said impedance adjustment circuit is to adjust said controllable impedance of said termination element in conjunction with adjusting first controllable impedance of said second load, and wherein said positive input terminal and said negative input terminal are coupled to said communication medium.
21. The apparatus of claim 19 , further comprising a communication medium, wherein said integrated circuit further comprises:
a low voltage differential signaling driver and a termination element connected between a positive output terminal of said driver and a negative output terminal of said driver, said termination element having a controllable impedance,
wherein said impedance adjustment circuit is to adjust said controllable impedance of said termination element in conjunction with adjusting said controllable impedance of said second load, and wherein said positive output terminal and said negative output terminal are coupled to said communication medium.
22. The apparatus of claim 12 , wherein said apparatus is a computer.
23. A method comprising:
generating a stabilized current;
generating a first supplementary current and a second supplementary current;
generating a controlled current in relation with said stabilized current;
forcing said stabilized current and said first supplementary current to flow through a first load; and
forcing said controlled current and said second supplementary current to flow through a second load.
24. The method of claim 23 , wherein generating said first supplementary current and said second supplementary current further comprises:
generating said first supplementary current and said second supplementary current
using substantially identical circuits.
25. The method of claim 23 , wherein generating said first supplementary current and said second supplementary current further comprises:
limiting said first supplementary current and said second supplementary current.
26. The method of claim 23 , wherein generating said first supplementary current and said second supplementary current further comprises:
switching said first supplementary current and said second supplementary current on and off.
27. The method of claim 23 , wherein generating said first supplementary current and said second supplementary current further comprises:
generating said first supplementary current and said second supplementary current using differential circuits.
28. The method of claim 23 , further comprising:
adjusting an impedance of said second load to minimize a difference between a first voltage drop across said first load and a second voltage drop across said second load.
29. The method of claim 28 , further comprising:
adjusting an impedance of a termination element in conjunction with adjusting said impedance of said second load, wherein said termination element is connected between terminals of a low voltage differential signaling driver.
30. The method of claim 28 , further comprising:
adjusting an impedance of a termination element in conjunction with adjusting said impedance of said second load, wherein said termination element is connected between terminals of a low voltage differential signaling receiver.