Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage
View Patent ↗A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.
1. A processor comprising:
an interface to non-volatile random access memory; and
logic circuitry to:
detect either of a start of a non-transactional operation to write to the non-volatile random access memory and a start of a transactional operation to enable a same specialized hardware that tracks a cache line change,
on detection of the start of the non-transactional operation, track, with the same specialized hardware that tracks the cache line change, a cache line written in the non-volatile random access memory for a modification by the non-transactional operation and write back a modified cache line to the non-volatile random access memory on detection of an end of the non-transactional operation, and
on detection of the start of the transactional operation, track, with the same specialized hardware that tracks the cache line change, a cache line written in the transactional operation and perform either of a commit and a roll back on detection of an end of the transactional operation.
2. The processor of claim 1 , wherein said non-volatile random access memory is phase-change memory (PCM).
3. The processor of claim 2 , wherein said non-volatile random access memory is phase-change memory and switch (PCMS).
4. The processor of claim 1 , further comprising an instruction execution pipeline to execute a first instruction to identify the start of the non-transactional operation to write to the non-volatile random access memory and execute a second instruction to identify the end of the non-transactional operation to write to the non-volatile random access memory.
5. The processor of claim 4 , further comprising cache flushing circuitry coupled to said instruction execution pipeline and said logic circuitry.
6. The processor of claim 5 , wherein said instruction execution pipeline is to not execute a next instruction until said end of the non-transactional operation to write to the non-volatile random access memory.
7. A method comprising:
detecting with a processor either of a start of a non-transactional operation to write to a non-volatile random access memory and a start of a transactional operation to enable a same specialized hardware of the processor that tracks a cache line change;
on detection of the start of the non-transactional operation, tracking, with the same specialized hardware that tracks the cache line change, a cache line written in the non-volatile random access memory for a modification by the non-transactional operation and write back a modified cache line to the non-volatile random access memory on detection of an end of the non-transactional operation; and
on detection of the start of the transactional operation, tracking, with the same specialized hardware that tracks the cache line change, a cache line written in the transactional operation and perform either of a commit and a roll back on detection of an end of the transactional operation.
8. The method of claim 7 , wherein execution of a first instruction causes the processor to identify the start of the non-transactional operation to write to the non-volatile random access memory and execution of a second instruction causes the processor to identify the end of the non-transactional operation to write to the non-volatile random access memory.
9. The method of claim 7 , wherein said non-volatile random access memory is implemented with phase-change memory (PCM).
10. The method of claim 9 , wherein said non-volatile random access memory is implemented with phase-change memory and switch (PCMS).
11. The method of claim 7 , further comprising not executing a next instruction until said end of the non-transactional operation to write to the non-volatile random access memory.
12. The method of claim 7 , further comprising disabling said same specialized hardware in response to either of the end of the non-transactional operation to write to the non-volatile random access memory and the end of the transactional operation.
13. A non-transitory machine readable storage medium having program code stored thereon that when processed by a computing system causes a method to be performed, said method comprising:
detecting with a processor either of a start of a non-transactional operation to write to a non-volatile random access memory and a start of a transactional operation to enable a same specialized hardware of the processor that tracks a cache line change;
on detection of the start of the non-transactional operation, tracking, with the same specialized hardware that tracks the cache line change, a cache line written in the non-volatile random access memory for a modification by the non-transactional operation and write back a modified cache line to the non-volatile random access memory on detection of an end of the non-transactional operation; and
on detection of the start of the transactional operation, tracking, with the same specialized hardware that tracks the cache line change, a cache line written in the transactional operation and perform either of a commit and a roll back on detection of an end of the transactional operation.
14. The non-transitory machine readable storage medium of claim 13 , wherein execution of a first instruction causes the processor to identify the start of the non-transactional operation to write to the non-volatile random access memory.
15. The non-transitory machine readable storage medium of claim 14 , wherein execution of a second instruction causes the processor to identify the end of the non-transactional operation to write to the non-volatile random access memory.
16. The non-transitory machine readable storage medium of claim 15 , wherein said second instruction causes said modified cache line to be flushed from one or more cache levels to said non-volatile random access memory.
17. The non-transitory machine readable storage medium of claim 13 , wherein the method further comprises not executing a next instruction until said end of the non-transactional operation to write to the non-volatile random access memory.
18. The non-transitory machine readable storage medium of claim 13 , wherein the processor comprises multiple cores each having the same specialized hardware that tracks the cache line change.
19. The non-transitory machine readable storage medium of claim 13 , wherein said non-volatile random access memory is phase-change memory (PCM).
20. The non-transitory machine readable storage medium of claim 19 , wherein said non-volatile random access memory is phase-change memory and switch (PCMS).