Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
1. An integrated circuit structure, comprising:
a nanowire above a substrate, the nanowire comprising a group III-V material;
a gate stack on and completely surrounding a channel region of the nanowire, the gate stack comprising:
a first dielectric layer on outer portions, but not an inner portion, of the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and on the inner portion of the channel region; and
a gate electrode on the second dielectric layer;
a bottom barrier layer between the substrate and the nanowire, wherein a bottom portion of the gate stack is on the bottom barrier layer; and
source and drain regions on either side of the gate stack.
2. The integrated circuit structure of claim 1 , wherein the source and drain regions are in the nanowire.
3. The integrated circuit structure of claim 1 , wherein the source and drain regions are above the nanowire.
4. The integrated circuit structure of claim 3 , further comprising:
a top barrier layer between the source and drain regions and the nanowire.
5. The integrated circuit structure of claim 1 , wherein the source and drain regions are on the nanowire.
6. The integrated circuit structure of claim 1 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
7. The integrated circuit structure of claim 6 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
8. The integrated circuit structure of claim 6 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (Zr O 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (Si O 2 ) and silicon nitride (Si 3 N 4 ).
9. The integrated circuit structure of claim 1 , wherein the first dielectric layer has a thickness approximately in the range of 2-15 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.
10. An integrated circuit structure, comprising:
a nanowire above a substrate, the nanowire comprising a group III-V material;
a gate stack on and completely surrounding a channel region of the nanowire, the gate stack comprising:
a first dielectric layer on the channel region;
a second, different, dielectric layer conformal with the first dielectric layer and on the first dielectric layer, but not on the channel region; and
a gate electrode on the second dielectric layer; and source and drain regions on either side of the gate stack.
11. The integrated circuit structure of claim 10 , wherein the source and drain regions are in the nanowire.
12. The integrated circuit structure of claim 10 , wherein the source and drain regions are above the nanowire.
13. The integrated circuit structure of claim 12 , further comprising:
a top barrier layer between the source and drain regions and the nanowire.
14. The integrated circuit structure of claim 10 , wherein the source and drain regions are on the nanowire.
15. The integrated circuit structure of claim 10 , further comprising: a bottom barrier layer between the substrate and the nanowire.
16. The integrated circuit structure of claim 15 , wherein a bottom portion of the gate stack is on the bottom barrier layer.
17. The integrated circuit structure of claim 10 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.
18. The integrated circuit structure of claim 17 , wherein the second dielectric layer has a dielectric constant greater than approximately 8 and the first dielectric layer has a dielectric constant approximately in the range of 4-8.
19. The integrated circuit structure of claim 17 , wherein the second dielectric layer comprises a material selected from the group consisting of tantalum silicon oxide (TaSiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO 2 ), zirconium oxide (Zr O 2 ), and lanthanum oxide (La 2 O 3 ), and the first dielectric layer comprises a material selected from the group consisting of aluminum silicate (AlSiO x ), silicon oxynitride (SiON), silicon dioxide (Si O 2 ) and silicon nitride (Si 3 N 4 ).
20. The integrated circuit structure of claim 10 , wherein the first dielectric layer has a thickness approximately in the range of 0.3-2 nanometers, and the second dielectric layer has a thickness approximately in the range of 0.5-3 nanometers.