Hybrid carbon-metal interconnect structures

1. A method comprising:

providing a substrate;

forming a metal interconnect layer on the substrate;

forming a graphene layer directly on the metal interconnect layer using the metal interconnect layer as a growth initiation layer for the graphene layer, the metal interconnect layer and the graphene layer being configured to route electrical signals; and

selectively removing metal of the metal interconnect layer subsequent to forming the graphene layer to form at least two metal interconnect structures in the metal interconnect layer that are electrically coupled by a suspended portion of the graphene layer.

2. The method of claim 1 , wherein:

providing the substrate comprises providing a substrate of an interposer that does not include any active transistor devices formed on the substrate and includes one or more passive devices formed on the substrate; and

forming the graphene layer comprises depositing one or more mono-layers of graphene nanoribbons (GNRs) on the metal interconnect layer at a temperature greater than or equal to 800° C.

3. The method of claim 1 , wherein forming the metal interconnect layer comprises depositing a metal, and the method further comprising:

forming a dielectric layer on the substrate; and

forming a barrier layer on the dielectric layer, wherein the barrier layer is disposed between the metal interconnect layer and the dielectric layer, the metal interconnect layer being in direct contact with the barrier layer.

4. The method of claim 3 , wherein:

forming the metal interconnect layer comprises depositing one or more of copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt) or palladium (Pd), the deposited metal having a (111) texture according to a convention (xyz), where x, y, and z represent respective crystallographic planes in three dimensions that are perpendicular to one another; and

forming the barrier layer comprises depositing tantalum (Ta); tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten nitride (WN) or ruthenium (Ru) using a physical vapor deposition (PVD) process.

5. The method of claim 3 , wherein the dielectric layer is a first dielectric layer, and the method further comprising:

patterning the metal interconnect layer to form a line structure;

forming a second dielectric layer on the graphene layer using a deposition process without oxygen plasma, radicals or ions, the second dielectric layer being in direct contact with the graphene layer; and

forming a third dielectric layer on the second dielectric layer, the third dielectric layer being in, direct contact with the second dielectric layer.

6. The method of claim 5 , wherein patterning the metal interconnect layer comprises:

depositing a first hardmask material on the graphene layer;

depositing a second hardmask material on the first hardmask material;

depositing a photodefinable material on the second hardmask material;

selectively removing portions of the photodefinable material;

etching the second hardmask material to remove portions of the second hardmask material that are not protected by the photodefinable material, the etching of the second hardmask material being selective to the first hardmask material;

removing the photodefinable material; and

subsequent to removing the photodefinable material, etching the first hardmask material, the graphene layer and the metal interconnect layer to remove portions of the first hardmask material, the graphene layer and the metal interconnect layer that are not protected by the second hardmask material.

7. The method of claim 5 , wherein:

forming the second dielectric layer comprises depositing silicon oxide using a sputtering or spin-on process or depositing silicon carbide, silicon carbonitride, or silicon nitride using an oxygen-free chemical vapor deposition (CVD) process; and

forming the third dielectric layer comprises depositing silicon oxide using a CVD process, wherein the second dielectric layer is configured to protect the graphene layer from oxygen plasma, radicals or ions during formation of the third dielectric layer.

8. The method of claim 5 , wherein forming the graphene layer comprises depositing graphene on sidewall surfaces of the metal interconnect layer.

9. The method of claim 5 , further comprising:

forming a via structure by removing material of the third dielectric layer and the second dielectric layer to form an opening that exposes the graphene layer; and

depositing electrically conductive material of the via structure on the exposed graphene layer, wherein electrically conductive material of the via structure terminates in the graphene layer.

10. The method of claim 5 , further comprising:

forming a via structure by removing material of the third dielectric layer, the second dielectric layer and the graphene layer to form an opening that exposes the metal interconnect layer; and

depositing electrically conductive material of the via structure into the opening on the exposed metal interconnect layer, wherein electrically conductive material of the via structure terminates in the metal interconnect layer.

11. The method of claim 10 , wherein:

depositing the electrically conductive material of the via structure comprises depositing carbon nanotubes (CNTs); and

forming the via structure further comprises depositing a dielectric material to encapsulate the CNTs, and the method further comprising:

performing a planarization process to provide a planar surface of the CNTs with the third dielectric layer, wherein depositing the dielectric, material to encapsulate the CNTs facilitates the planarization process of the CNTs.

12. The method of claim 1 , wherein at least one of the two metal interconnect structures is a bond pad, and the method further comprising

depositing a dielectric material to fill a region between the suspended portion of the graphene layer and the substrate where the metal of the metal interconnect layer has been removed; and

forming a bump or pillar on and electrically coupled with the bond pad.

13. A method comprising:

providing a substrate;

forming a metal interconnect layer on the substrate; and

forming a graphene layer directly on the metal interconnect layer using the metal interconnect layer as a growth initiation layer for the graphene layer, the metal interconnect layer and the graphene layer being configured to route electrical signals,

wherein providing the substrate comprises providing a substrate of an interposer that does not include any active transistor devices formed on the substrate and includes one or more passive devices formed on the substrate, and

wherein forming the graphene layer comprises depositing one or more mono-layers of graphene nanoribbons (GNRs) on the metal interconnect layer at a temperature greater than or equal to 800° C.

14. The method of claim 13 , wherein forming the metal interconnect layer comprises depositing a metal, and the method further comprising:

forming a dielectric layer on the substrate; and

forming a barrier layer on the dielectric layer, wherein the barrier layer is disposed between the metal interconnect layer and the dielectric layer, the metal interconnect layer being in direct contact with the barrier layer.

15. The method of claim 14 , wherein:

forming the metal interconnect layer comprises depositing one or more of copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt) or palladium (Pd), the deposited metal having a (111) texture according to a convention (xyz), where x, y, and z represent respective crystallographic planes in three dimensions that are perpendicular to one another; and

forming the barrier layer comprises depositing tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tungsten nitride (WN) or ruthenium (Ru) using a physical vapor deposition (PVD) process.

16. The method of claim 14 , wherein the dielectric layer is a first dielectric layer, and the method further comprising:

patterning the metal interconnect layer to form a line structure;

forming a second dielectric layer on the graphene layer using a deposition process without oxygen plasma, radicals or ions, the second dielectric layer being in direct contact with the graphene layer; and

forming a third dielectric layer on the second dielectric layer, the third dielectric layer being in direct contact with the second dielectric layer.

17. The method of claim 16 , wherein patterning the metal interconnect layer comprises:

depositing a first hardmask material on the graphene layer;

depositing a second hardmask material on the first hardmask material;

depositing a photodefinable material on the second hardmask material;

selectively removing portions of the photodefinable material;

etching the second hardmask material to remove portions of the second hardmask material that are not protected by the photodefinable material, the etching of the second hardmask material being selective to the first hardmask material;

removing the photodefinable material; and

subsequent to removing the photodefinable material, etching the first hardmask material, the graphene layer and the metal interconnect layer to remove portions of the first hardmask material, the graphene layer and the metal interconnect layer that are not protected by the second hardmask material.

18. The method of claim 16 , wherein:

forming the second dielectric, layer comprises depositing silicon oxide using a sputtering or spin-on process or depositing silicon carbide, silicon carbonitride, or silicon nitride using an oxygen-free chemical vapor deposition (CVD) process; and

forming the third dielectric layer comprises depositing silicon oxide using a CVD process, wherein the second dielectric layer is configured to protect the graphene layer from oxygen plasma, radicals or ions during formation of the third dielectric layer.

19. The method of claim 16 , wherein forming the graphene layer comprises depositing graphene on sidewall surfaces of the metal interconnect layer.

20. The method of claim 16 , further comprising:

forming a via structure by removing material of the third dielectric layer and the second dielectric layer to form an opening that exposes the graphene layer; and

depositing electrically conductive material of the via structure on the exposed graphene layer, wherein electrically conductive material of the via structure terminates in the graphene layer.

21. The method of claim 16 , further comprising:

forming a via structure by removing material of the third dielectric layer, the second dielectric layer and the graphene layer to form an opening that exposes the metal interconnect layer; and

depositing electrically conductive material of the via structure into the opening on the exposed metal interconnect layer, wherein electrically conductive material of the via structure terminates in the metal interconnect layer.

22. The method of claim 21 , wherein:

depositing the electrically conductive material of the via structure comprises depositing carbon nanotubes (CNTs); and

forming the via structure further comprises depositing a dielectric material to encapsulate the CNTs, and the method further comprising:

performing a planarization process to provide a planar surface of the CNTs with the third dielectric layer, wherein depositing the dielectric material to encapsulate the CNTs facilitates the planarization process of the CNTs.

23. The method of claim 13 , further comprising:

selectively removing metal of the metal interconnect layer subsequent to forming the graphene layer to form at least two metal interconnect structures in the metal interconnect layer that are electrically coupled by a suspended portion of the graphene layer.

24. The method of claim 23 , wherein at least one of the two metal interconnect structures is a bond pad, and the method flintier comprising:

depositing a dielectric material to fill a region between the suspended portion of the graphene layer and the substrate where the metal of the metal interconnect layer has been removed; and

forming a bump or pillar on and electrically coupled with the bond pad.