Interlayer dielectric for non-planar transistors

Inventors: Sameer Pradhan (Portland, OR); Jeanne Luce (Hillsboro, OR)

Assignee: Intel Corporation

H01L29/7851 H01L21/0234 H01L21/02304 H01L21/02323 H01L21/02337 H01L21/02356 H01L21/76826 H01L21/76829 H01L21/76897 H01L21/823431 H01L29/66545 H01L29/66575 H01L29/66795 H01L29/785 H01L29/7843 H01L29/7848 H01L21/02282 H01L21/76834

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Quick Facts

Patent No.: US 10,693,006
App. No.: 16/040,053
Granted: Jun 23, 2020
Kind: B2

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Abstract

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Claims (20)

1. An integrated circuit (IC) structure, comprising: a fin having a source and a drain; a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode; a capping structure over the gate electrode; spacers on the pair of sidewalls; an adhesion liner contacting the spacers; and a dielectric layer contacting the adhesion liner, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner.

2. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an annealed portion of the dielectric layer.

3. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an oxidized portion of the dielectric layer.

4. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an annealed and oxidized portion of the dielectric layer.

5. The integrated circuit (IC) structure of claim 1 , further comprising a contact extending through the dielectric layer to one of the source and the drain.

6. The integrated circuit (IC) structure of claim 1 , wherein the fin comprises silicon.

7. The integrated circuit (IC) structure of claim 1 , wherein the capping structure comprises silicon and nitrogen.

8. The integrated circuit (IC) structure of claim 7 , wherein the capping structure comprises silicon nitride.

9. The integrated circuit (IC) structure of claim 1 , wherein the dielectric layer comprises silicon and oxygen.

10. The integrated circuit (IC) structure of claim 9 , wherein the dielectric layer comprises silicon oxide.

11. The integrated circuit (IC) structure of claim 1 , wherein the transistor gate is non-planar.

12. The integrated circuit (IC) structure of claim 1 , wherein the source and the drain are non-planar.

13. A method of forming an integrated circuit (IC) structure, comprising: forming a fin; forming a source and a drain in the fin; forming a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode; forming a capping structure over the gate electrode; forming spacers on the pair of sidewalls; forming an adhesion liner contacting the spacers; forming a dielectric layer contacting the adhesion liner; and forming a densified portion of the dielectric layer resulting in a densified portion of the dielectric layer and a non-densified portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner.

14. The method of claim 13 , wherein forming the densified portion of the dielectric layer comprises annealing the portion of the dielectric.

15. The method of claim 14 , wherein annealing the portion of the dielectric layer comprises annealing the dielectric layer with high density plasma in an inert atmosphere.

16. The method of claim 13 , wherein forming the densified portion of the dielectric layer comprises oxidizing the portion of the dielectric layer.

17. The method of claim 16 , wherein oxidizing the portion of the dielectric layer comprises heating the dielectric layer in a steam atmosphere.

18. The method of claim 13 , wherein forming the densified portion of the dielectric layer comprises oxidizing and annealing the portion of the dielectric layer.

19. The method of claim 13 , further comprising forming a contact extending through the dielectric layer to one of the source and the drain.

20. The method of claim 13 , wherein forming the dielectric layer comprises forming the dielectric layer comprising silicon and oxygen.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022

From: INTEL CORPORATION

To: TAHOE RESEARCH, LTD.

Reel/Frame 061175/0176 →