Hardware apparatuses and methods to control access to a multiple bank data cache
View Patent ↗Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
1. A hardware apparatus comprising:
conflict resolution circuit to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
2. The hardware apparatus of claim 1 , wherein the conflict resolution circuit is to grant the access priority to the instruction with a largest access width.
3. The hardware apparatus of claim 2 , wherein a queue entry for each of the multiple instructions include an access width.
4. The hardware apparatus of claim 1 , wherein the conflict resolution circuit is to grant access priority to an earliest instruction when the multiple instructions are scheduled to access a same total of banks of the multiple bank data cache.
5. The hardware apparatus of claim 4 , wherein a queue entry for each of the multiple instructions include a relative program order.
6. The hardware apparatus of claim 1 , wherein an instruction of the multiple instructions that is not to be granted access priority is to be redispatched to the conflict resolution circuit.
7. The hardware apparatus of claim 1 , wherein the conflict resolution circuit is to detect the multiple instructions scheduled to access the same bank of the multiple bank data cache in the same clock cycle by comparing a bank access mask of each of a plurality of instructions.
8. The hardware apparatus of claim 1 , wherein the conflict resolution circuit is to grant access to the multiple bank data cache to multiple instructions that are not scheduled to access the same bank of the multiple bank data cache in the same clock cycle.
9. A method to control access to a multiple bank data cache comprising:
detecting multiple instructions scheduled to access a same bank of the multiple bank data cache in a same clock cycle; and
granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
10. The method of claim 9 , wherein the granting comprises granting the access priority to the instruction with a largest access width.
11. The method of claim 10 , further comprising providing a queue entry for each of the multiple instructions that includes an access width.
12. The method of claim 9 , wherein the granting comprises granting access priority to an earliest instruction when the multiple instructions are scheduled to access a same total of banks of the multiple bank data cache.
13. The method of claim 12 , further comprising providing a queue entry for each of the multiple instructions that include a relative program order.
14. The method of claim 9 , further comprising redispatching an instruction of the multiple instructions that is not to be granted access priority.
15. The method of claim 9 , wherein the detecting comprises comparing a bank access mask of each of a plurality of instructions.
16. The method of claim 9 , further comprising granting access to the multiple bank data cache to multiple instructions that are not scheduled to access the same bank of the multiple bank data cache in the same clock cycle.
17. A hardware system comprising:
a core to execute a plurality of instructions in a same clock cycle; and
conflict resolution circuit to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in the same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
18. The hardware system of claim 17 , wherein the conflict resolution circuit is to grant the access priority to the instruction with a largest access width.
19. The hardware system of claim 18 , wherein a queue entry for each of the multiple instructions include an access width.
20. The hardware system of claim 17 , wherein the conflict resolution circuit is to grant access priority to an earliest instruction when the multiple instructions are scheduled to access a same total of banks of the multiple bank data cache.
21. The hardware system of claim 20 , wherein a queue entry for each of the multiple instructions include a relative program order.
22. The hardware system of claim 17 , wherein an instruction of the multiple instructions that is not to be granted access priority is to be redispatched to the conflict resolution circuit.
23. The hardware system of claim 17 , wherein the conflict resolution circuit is to detect the multiple instructions scheduled to access the same bank of the multiple bank data cache in the same clock cycle by comparing a bank access mask of each of the plurality of instructions.
24. The hardware system of claim 17 , wherein the conflict resolution circuit is to grant access to the multiple bank data cache to multiple instructions that are not scheduled to access the same bank of the multiple bank data cache in the same clock cycle.