Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage
A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.
1. A processor comprising:
an interface to non-volatile memory;
logic circuitry to track, with a same specialized hardware that tracks a cache line change, a cache line written in a transactional operation and perform either of a commit and a roll back at an end of the transactional operation; and
an execution unit to execute a first instruction to cause the same specialized hardware that tracks the cache line change to track a cache line written in the non-volatile memory for a modification by a non-transactional operation.
2. The processor of claim 1 , wherein the non-volatile memory is phase-change memory (PCM).
3. The processor of claim 1 , wherein the execution unit is to execute a second instruction to identify an end of the non-transactional operation to cause a write back of a modified cache line to the non-volatile memory.
4. The processor of claim 3 , further comprising cache flushing circuitry coupled to the execution unit and the logic circuitry.
5. The processor of claim 3 , wherein the execution unit is to not execute a next instruction until the end of the non-transactional operation.
6. The processor of claim 1 , wherein the execution unit is to execute a second instruction to cause a write back of a modified cache line to the non-volatile memory.
7. The processor of claim 6 , wherein the execution unit is to execute the second instruction to disable the same specialized hardware after the write back.
8. A method comprising:
tracking, with a same specialized hardware of a processor that tracks a cache line change, a cache line written in a transactional operation;
performing either of a commit and a roll back at an end of the transactional operation; and
executing a first instruction with an execution unit of the processor to cause the same specialized hardware that tracks the cache line change to track a cache line written in a non-volatile memory for a modification by a non-transactional operation.
9. The method of claim 8 , wherein the non-volatile memory is phase-change memory (PCM).
10. The method of claim 8 , further comprising executing a second instruction with the execution unit of the processor to identify an end of the non-transactional operation to cause a write back of a modified cache line to the non-volatile memory.
11. The method of claim 10 , further comprising not executing a next instruction until the end of the non-transactional operation.
12. The method of claim 8 , further comprising executing a second instruction with the execution unit of the processor to cause a write back of a modified cache line to the non-volatile memory.
13. The method of claim 12 , wherein the executing the second instruction is to disable the same specialized hardware after the write back.
14. The method of claim 13 , further comprising disabling the same specialized hardware in response to the end of the transactional operation.
15. A non-transitory machine readable storage medium having program code stored thereon that when processed by a computing system causes a method to be performed, the method comprising:
tracking, with a same specialized hardware of a processor that tracks a cache line change, a cache line written in a transactional operation;
performing either of a commit and a roll back at an end of the transactional operation; and
executing a first instruction with an execution unit of the processor to cause the same specialized hardware that tracks the cache line change to track a cache line written in a non-volatile memory for a modification by a non-transactional operation.
16. The non-transitory machine readable storage medium of claim 15 , wherein the non-volatile memory is phase-change memory (PCM).
17. The non-transitory machine readable storage medium of claim 15 , wherein the method further comprises executing a second instruction with the execution unit of the processor to identify an end of the non-transactional operation to cause a write back of a modified cache line to the non-volatile memory.
18. The non-transitory machine readable storage medium of claim 17 , wherein the method further comprises not executing a next instruction until the end of the non-transactional operation.
19. The non-transitory machine readable storage medium of claim 15 , wherein the method further comprises executing a second instruction with the execution unit of the processor to cause a write back of a modified cache line to the non-volatile memory.
20. The non-transitory machine readable storage medium of claim 19 , wherein the executing the second instruction is to disable the same specialized hardware after the write back.
21. The non-transitory machine readable storage medium of claim 20 , wherein the method further comprises disabling the same specialized hardware in response to the end of the transactional operation.