Monitor implementation in a multicore processor with inclusive LLC
View Patent ↗A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.
1. A method comprising:
issuing, for a requesting core in a multi-core system having a shared cache, a monitor transaction;
detecting the monitor transaction;
determining bit status in the shared cache for the request core including detecting a coherence state for the shared cache and a core bit status of an issuing core for the requesting core;
completing the monitor transaction without sending a self-snoop to the requesting core based on the core bit status of the issuing core, and receiving a last level cache (LLC) grant signal.
2. The method of claim 1 , further comprising receiving a LLC HIT signal.
3. The method of claim 2 wherein the LLC HIT signal indicates the coherency state.
4. The method of claim 1 , wherein completing the monitor transaction comprises sending out a global observation signal to requesting core.
5. The method of claim 1 , further comprising issuing a cross snoop transaction.
6. The method of claim 5 wherein issuing a cross snoop transaction includes ensuring other cores are not prohibiting access to the shared cache.
7. The method of claim 1 , further comprising determining if the requesting core does not contain cache line.
8. A system comprising:
a bridge; and
one or more cores coupled to the bridge, the bridge including a shared cache and control logic, wherein the bridge is to detect a monitor transaction, determine bit status in the shared cache for the requesting core including detecting a coherency state for the shared cache and a core bit status of an issuing core for a requesting core, completing the monitor transaction without sending a self-snoop to the requesting core based on the core bit status of the issuing core, and receiving a last level cache (LLC) grant signal.
9. The system of claim 8 wherein the bridge indicates a last level cache (LLC) HIT signal to indicate the coherency state.
10. The system of claim 8 , wherein the bridge is to send out a global observation signal to the issuing core.
11. The system of claim 8 , wherein the bridge issues a cross snoop transaction to indicate the coherency state.
12. The system of claim 8 , wherein the bridge is to determine if the issuing core does not contain cache line.