Integrating n-type and p-type metal gate transistors
View Patent ↗At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
1. A process comprising:
forming an n-type and p-type translator upon a semiconductor substrate, the n-type and p-type transistors comprising n-type and p-type polysilicon gates, respectively forming ILD 0 on top of the n-type and p-type transistors:
etching the n-type polysillcon gate to form a first trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on the bottom of the first trench;
depositing n-type metal into the first trench, wherein the n-type metal gate is to be doped by implanting n-type material after the metal gate has been deposited in the first trench;
removing excess n-type gate material to expose the top of the n-type metal gate and the p-type polysilicon gate;
etching the p-type polysilicon gate to form a second trench bound in part by substantially vertical lateral side-wall spacers and a gate dielectric on the bottom of the second trench;
depositing a p-type metal gate within the second trench;
removing excess n-type gate material to expose the top of the n-type metal gate and the p-type metal gate.
2. The process of claim 1 further comprising removing an ILD 0 lever from the top of the polysillcon gates.
3. The process of claim 2 further comprising forming source, gate, and drain contacts to the n-type and p-type transistors.
4. The process of claim 1 wherein the n-type metal gate is selected from a group consisting of Hf, Zr, Ti, Ta, and Al.
5. The process of claim 1 wherein the p-type metal gate is selected from a group consisting of Ru, Pd, Pt, Co, Ni, TiAlN and WCN.
6. The process of claim 1 wherein the p-type metal gate and the n-type metal gate is at least 50 and no greater than 1000 angstroms thick.
7. The process of claim 1 wherein etching the n-type and p-type polysilicon gates is an ammonium hydroxide etch.
8. The process of claim 1 wherein etching the n-type and p-type polysillcon gates is performed by using a wet etch.
9. The process of claim 1 wherein the p-type metal gate is doped by implanting the metal gate with p-type material after the metal gate has been deposited into the second trench.