Non-volatile register file including memory cells having conductive oxide memory element
Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
1. An apparatus comprising:
a memory element included in a non-volatile memory cell, the memory element including a conductive oxide material located over a substrate;
a transistor including a drain;
a connection formed from a same conductive material directly coupled between the drain of the transistor and a first portion of the conductive oxide material of the memory element:
an access line coupled to a gate to the transistor, the access line having a length extending in a first direction and located between the substrate and the memory element;
a first conductive line coupled to a source of the transistor, the first conductive line having a length extending in a second direction and located between the access line and the memory element; and
a second conductive line coupled to a second portion of the conductive oxide material of the memory element, the second conductive line having a length extending in the second direction, wherein the memory element is located between the first and second conductive lines.
2. The apparatus of claim 1 , wherein the non-volatile memory cell is included in a register file, and the transistor is arranged to form part of a conductive path between the first and second conductive lines during a write operation of the register file.
3. The apparatus of claim 1 , wherein the non-volatile memory cell is included in a register file, and the transistor is arranged to form part of a conductive path between the first and second conductive lines during a read operation of the register file.
4. The apparatus of claim 1 , wherein the same conductive material of the connection includes polysilicon.
5. The apparatus of claim 1 , further comprising an additional connection of a same material, the additional connection directly coupled between the second conductive line and the second portion of the conductive oxide material of the memory element, such that the second conductive line is coupled to the second portion of the conductive oxide material of the memory element through the additional connection.
6. The apparatus of claim 5 , wherein the same conductive material of the additional connection includes polysilicon.
7. The apparatus of claim 1 , further comprising a via, wherein:
the first conductive line is located on a first level of the apparatus;
the second conductive line is located on a second level of the apparatus;
the via is located on a level between the first and second levels;
the first portion of the conductive oxide material of the memory element is inside the via; and
the second portion of the conductive oxide material of the memory element is inside the via.
8. An apparatus comprising:
a memory element included in a non-volatile memory cell, the memory element including a conductive oxide material located over a substrate;
a transistor including a drain coupled to a first portion of the memory element;
an access line coupled to a gate to the transistor, the access line having a length extending in a first direction and located between the substrate and the memory element;
a first conductive line coupled to a source of the transistor, the first conductive line having a length extending in a second direction and located between the access line and the memory element; and
a second conductive line coupled to a second portion of the memory element, the second conductive line having a length extending in the second direction, wherein the memory element is located between the first and second conductive lines, wherein the first conductive line is located on a first level of the apparatus, the second conductive line is located on a second level of the apparatus, at least a portion of the memory element is inside a via, and the via is located on a level between the first and second levels.
9. An apparatus comprising:
a memory element included in a non-volatile memory cell, the memory element including a conductive oxide material located over a substrate,
a transistor including a drain coupled to a first portion of the memory element:
an access line coupled to a gate to the transistor, the access line having a length extending in a first direction and located between the substrate and the memory element,
a first conductive line coupled to a source of the transistor, the first conductive line having a length extending in a second direction and located between the access line and the memory element,
a second conductive line coupled to a second portion of the memory element, the second conductive line having a length extending in the second direction, wherein the memory element is located between the first and second conductive lines; further comprising:
a first additional transistor coupled in series with the memory element between the second conductive line and a first data line;
a second additional transistor coupled in series with the memory element between the second conductive line and a second data line; and
a third additional transistor coupled in series with the memory element between the second conductive line and a third data line.
10. The apparatus of claim 9 , wherein the memory element, the transistor, and the first, second, and third additional transistors are arranged to allow the non-volatile memory cell to operate as a non-volatile memory cell having multiple input/output ports.
11. The apparatus of claim 9 , wherein the second data line and the third data line are located on the same level of the apparatus.
12. The apparatus of claim 9 , wherein:
the first data line is located on a first level of the apparatus;
the second data line is located on a second level of the apparatus different from the first level of the apparatus; and
the third data line is located on the same second level of the apparatus as the second data line.
13. The apparatus of claim 9 , wherein the first, second, and third data lines have lengths extending in a same direction.
14. The apparatus of claim 9 , wherein:
the first additional transistor includes a doped region coupled to the second portion of the memory element;
the second additional transistor includes a doped region coupled to the second portion of the memory element; and
the third additional transistor includes a doped region coupled to the second portion of the memory element.
15. The apparatus of claim 14 , wherein the doped region of the first additional transistor is the same as the doped region of the second additional transistor.