Method for making a semiconductor device having a high-k gate dielectric
View Patent ↗A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
1. A method for making a semiconductor device comprising:
forming a silicon dioxide layer on a substrate;
forming a high-k dielectric layer on the silicon dioxide layer;
forming a capping layer on the high-k dielectric layer; and
exposing the silicon dioxide layer and the high-k dielectric layer to ammonia at a temperature of at least about 650° C. for at least about 1 minute to generate a gate dielectric with a graded dielectric constant; and
removing the capping layer after annealing the silicon dioxide layer and the high-k dielectric layer.
2. The method of claim 1 wherein the silicon dioxide layer is less than about 10 angstroms thick, and is formed by exposing the substrate to hydrofluoric acid, then to a first aqueous solution that comprises hydrogen peroxide and ammonium hydroxide, and then to a second aqueous solution that comprises hydrogen peroxide and hydrogen chloride.
3. The method of claim 1 wherein the high-k dielectric layer is less than about 40 angstroms thick, and comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
4. The method of claim 1 wherein the silicon dioxide layer and the high-k dielectric layer are exposed to ammonia at a temperature that is between about 650° C. and about 900° C. for between about 1 minute and about 10 minutes.
5. The method of claim 1 wherein the capping layer comprises a metal that is selected from the group consisting of a metallic nitride, hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel and a conductive metal oxide.
6. A method for making a semiconductor device comprising:
forming a silicon dioxide layer on a substrate;
forming a high-k dielectric layer on said silicon dioxide layer;
forming a sacrificial capping layer on said high-k dielectric layer; and
subsequent to forming said sacrificial capping layer, annealing said silicon dioxide layer and said high-k dielectric layer at a sufficient temperature and for a sufficient time to generate a gate dielectric with a graded dielectric constant; and
removing said sacrificial capping layer.
7. The method of claim 6 wherein said high-k dielectric layer is less than about 40 angstroms thick and comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.
8. The method of claim 7 wherein said sacrificial capping layer comprises a metal that is selected from the group consisting of a metallic nitride, hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel and a conductive metal oxide.
9. The method of claim 6 wherein said gate dielectric with said graded dielectric constant comprises a bottom surface like said silicon dioxide layer, a top surface like said high-k dielectric layer and a graded silicate in between.
10. The method of claim 6 wherein said sacrificial capping layer is removed by applying a wet etch process that is selective for said sacrificial capping layer over said gate dielectric with said graded dielectric constant.
11. A method for making a semiconductor device comprising:
forming a silicon dioxide layer on a substrate; and
subsequent to forming said silicon dioxide layer, forming a high-k dielectric layer on said silicon dioxide layer; and
subsequent to forming said high-k dielectric layer, forming a capping layer on said high-k dielectric layer; and
subsequent to forming said capping layer, annealing said silicon dioxide layer, said high-k dielectric layer and said capping layer at a sufficient temperature and for a sufficient time to generate a gate dielectric with a graded dielectric constant; and
subsequent to annealing said silicon dioxide layer, said high-k dielectric layer and said capping layer, removing said capping layer.
12. The method of claim 11 wherein said gate dielectric with said graded dielectric constant comprises a bottom surface like said silicon dioxide layer, a top surface like said high-k dielectric layer and a graded silicate in between.
13. The method of claim 11 wherein said capping layer is removed by applying a wet etch process that is selective for said capping layer over said gate dielectric with said graded dielectric constant.
14. The method of claim 11 wherein said silicon dioxide layer, said high-k dielectric layer and said capping layer are annealed in the presence of ammonia at a temperature of at least about 650° C. for at least about 1 minute.