High density interconnect device and method
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
1. A microelectronic die comprising:
a high density interconnect located adjacent to a first edge on a first surface, the high density interconnect having a first bump pitch, the high density interconnect bump pitch sized to connect to an interconnecting bridge;
a connection region located adjacent to a second edge on the first surface, the connection region having a second bump pitch, wherein the second bump pitch is a direct chip attach (DCA) pitch sized to attach to a circuit board; and
a power connection region located on the first surface interior to the high density interconnect and the connection region.
2. The die of claim 1 , wherein the first bump pitch is from about 30 μm to about 90 μm.
3. The die of claim 1 , wherein the connection region includes power connections.
4. The die of claim 1 , wherein the connection region includes input/output connections.
5. The die of claim 1 , wherein the die is a System On Chip (SOC) die.
6. The die of claim 1 , wherein the die is a memory die.
7. The die of claim 1 , wherein the first bump pitch is less than the second bump pitch.
8. The die of claim 1 , wherein the first bump pitch is less than the second bump pitch, and wherein the first bump pitch is from about 30 μm to about 90 μm.
9. A microelectronic die comprising:
a high density interconnect located adjacent to a first edge on a first surface, the high density interconnect having a first bump pitch, the high density interconnect bump pitch sized to connect to an interconnecting bridge;
a connection region located adjacent to a second edge on the first surface, the connection region having a second bump pitch; and
a power connection region located on the first surface interior to the high density interconnect and the connection region.
10. The die of claim 9 , wherein the first bump pitch is less than the second bump pitch.
11. The die of claim 9 , wherein the second bump pitch is less than a power connection region bump pitch.
12. The die of claim 9 , wherein the second bump pitch is about equal to a power connection region bump pitch.
13. The die of claim 9 , wherein the second bump pitch is a direct chip attach (DCA) pitch sized to attach to a circuit board.
14. The die of claim 9 , wherein the connection region located adjacent to the second edge on the first surface includes input/output connections.
15. A microelectronic die comprising:
a high density interconnect located adjacent to a first edge on a first surface, the high density interconnect having a first bump pitch, the high density interconnect bump pitch sized to connect to an interconnecting bridge;
a connection region on the first surface, the connection region having a second bump pitch, wherein the second bump pitch is a direct chip attach (DCA) pitch sized to attach to a circuit board; and
a power connection region located on the first surface interior to the high density interconnect and the connection region.
16. The die of claim 15 , wherein bumps of the connection region having the second bump pitch are located adjacent to a second edge on the first surface of the die.
17. The die of claim 15 , wherein the connection region includes power connections.
18. The die of claim 17 , wherein the connection region includes input/output connections.