Systems and methods for accessing a unified translation lookaside buffer
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.
1. A method for accessing a unified translation lookaside buffer (TLB), comprising:
searching a page size cache mapping virtual addresses to page sizes for an input virtual address to identify a page size; and
looking up a physical address translation of the virtual address in a second level TLB using the page size.
2. The method of claim 1 , wherein searching the page size cache is in response to a miss of the virtual address in a level one TLB (L1TLB).
3. The method of claim 1 wherein searching the page size cache and looking up the physical address is performed in a single clock cycle.
4. The method of claim 1 wherein the page size determines bits of the virtual address that are translated to form the physical address.
5. The method of claim 1 wherein the page size determines bits of the virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.
6. The method of claim 1 wherein a search of the second level TLB based on the page size is executed to find a physical address wherein said second level TLB is of n-way associativity.
7. The method of claim 1 wherein the page size is a correct size of the page that is associated with the physical address.
8. The method of claim 1 wherein the page size cache does not provide virtual address to physical address translation.
9. A unified translation lookaside buffer (TLB), comprising:
a page size cache mapping virtual addresses to page size;
a second level TLB mapping virtual addresses and page sizes to physical addresses; and
a unified TLB access component to search the page size cache with an input virtual address to identify a page size, and to look up a physical address translation of the virtual address in the second level TLB using the page size.
10. The unified TLB of claim 9 , further comprising:
a level one TLB (L1TLB).
11. The unified TLB of claim 10 , wherein the unified TLB access component is further to search the page size cache in response to a miss of the input virtual address in the level one TLB (L1TLB).
12. The unified TLB of claim 9 , wherein unified TLB access component searches the page size cache and looks up the physical address in a single clock cycle.
13. The unified TLB of claim 9 , wherein the page size determines the bits of virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.
14. The unified TLB of claim 9 wherein the second level TLB is of n-way associativity.
15. The unified TLB of claim 9 wherein the page size is a correct size of the page that is associated with the physical address.
16. A computer system comprising:
a processor;
a memory;
a memory management unit (MMU) coupled to the processor and the memory, the MMU to access memory in response to requests from the processor; and
a unified translation lookaside buffer (TLB) to convert virtual addresses provided by the MMU into physical addresses in the memory, the unified TLB including a page size cache mapping virtual addresses to page size, a second level TLB mapping virtual addresses and page sizes to physical addresses, and a unified TLB access component to search the page size cache with an input virtual address to identify a page size, and to look up a physical address translation of the virtual address in the second level TLB using the page size.
17. The computer system of claim 16 , wherein the unified TLB further comprises:
a level one TLB (L1TLB).
18. The computer system of claim 17 , wherein the unified TLB access component is further to search the page size cache in response to a miss of the input virtual address in the level one TLB (L1TLB).
19. The computer system of claim 16 , wherein unified TLB access component searches the page size cache and looks up the physical address in a single clock cycle.
20. The computer system of claim 16 , wherein the page size determines bits of the virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.