Nanoscale structure with epitaxial film having a recessed bottom portion
View Patent ↗An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.
1. An apparatus comprising:
a substrate having a first lattice constant;
an epitaxial (EPI) layer, having a second lattice constant different from the first lattice constant, including a bottom portion and opposing sidewall portions;
a transistor channel including the EPI layer; and
a fin on the substrate;
wherein (a) the bottom portion includes a recess in-between the opposing sidewall portions, (b) the recess does not include the fin but does include a dielectric material, and (c) a horizontal axis, parallel to the substrate, intersects the recess, the dielectric material, and the opposing sidewall portions.
2. The apparatus of claim 1 , wherein the recess is collinear with a long axis of the fin.
3. The apparatus of claim 1 , wherein the bottom portion includes the recess and the recess is formed by the fin.
4. The apparatus of claim 1 wherein the fin is monolithic with the substrate.
5. The apparatus of claim 1 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the middle portion has a first width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
at least one of the upper and bottom portions includes a second width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
the first width is greater than the second width.
6. The apparatus of claim 5 wherein:
at least another of the upper and bottom portions includes a third width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
the first width is greater than the third width.
7. The apparatus of claim 1 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the opposing sidewall portions taper towards each other as they progress from the middle portion towards the bottom portion.
8. The apparatus of claim 1 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the opposing sidewall portions taper towards each other as they progress from the middle portion towards the upper portion.
9. The apparatus of claim 1 comprising a gate electrode that surrounds the EPI layer in a vertical plane that is orthogonal to the substrate.
10. The apparatus of claim 1 comprising a gate electrode between the bottom portion and the substrate, wherein a vertical axis that is orthogonal to the substrate intersects the gate electrode and the EPI layer.
11. The apparatus of claim 1 wherein the dielectric material contacts the opposing sidewall portions.
12. The apparatus of claim 1 wherein the recess is not completely filled with material.
13. The apparatus of claim 1 wherein:
the EPI layer has a first width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
the EPI layer has a second width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
the first and second widths are unequal to each other;
the first and second widths are measured horizontally and parallel to the substrate.
14. An apparatus comprising:
a substrate having a first lattice constant;
an epitaxial (EPI) layer, having a second lattice constant different from the first lattice constant, including a bottom portion and opposing sidewall portions;
a fin; and
a gate electrode between the bottom portion and the substrate;
wherein (a) the bottom portion includes a recess, (b) the recess does not include the fin, and (c) a vertical axis that is orthogonal to the substrate intersects the gate electrode and the EPI layer.
15. The apparatus of claim 14 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the middle portion has a first width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
at least one of the upper and bottom portions includes a second width extending from one of the opposing sidewall portions to another of the opposing sidewall portions;
the first width is greater than the second width.
16. The apparatus of claim 14 wherein the recess includes a dielectric material.
17. An apparatus comprising:
a substrate having a first lattice constant;
an epitaxial (EPI) layer, having a second lattice constant different from the first lattice constant, including a bottom portion and opposing sidewall portions;
a transistor channel including the EPI layer; and
a fin on the substrate;
wherein (a) the bottom portion includes a recess, (b) the recess does not include the fin, and (c) the recess is not completely filled with material.
18. The apparatus of claim 17 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the opposing sidewall portions taper towards each other as they progress from the middle portion towards the bottom portion.
19. The apparatus of claim 17 wherein:
the EPI layer has an upper portion and a middle portion;
the middle portion is between the upper portion and the bottom portion;
the opposing sidewall portions taper towards each other as they progress from the middle portion towards the upper portion.
20. The apparatus of claim 17 comprising a gate electrode between the bottom portion and the substrate, wherein a vertical axis that is orthogonal to the substrate intersects the gate electrode and the EPI layer.