Forming a non-planar transistor having a quantum well channel
View Patent ↗In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
1. A method comprising:
forming a buried oxide layer directly on a substrate;
forming a semiconductor fin comprising a silicon on insulator core directly on the buried oxide layer, the semiconductor fin providing a channel region for a non-planar field effect transistor (FET);
forming a first semiconductor layer comprising silicon germanium (SiGe) directly on and wrapped around the semiconductor fin and directly contacting at least a portion of the buried oxide layer, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin, the SiGe having a Ge concentration of at least approximately 10%;
forming a second semiconductor layer comprising tensile strained silicon directly on and wrapped around the first semiconductor layer;
forming a dielectric layer adjacent the second semiconductor layer; and
forming a gate electrode adjacent the dielectric layer, the gate electrode and the dielectric layer directly contacting at least a portion of the buried oxide layer.
2. The method of claim 1 , further comprising providing a quantum well for holes via the first semiconductor layer.
3. The method of claim 2 , further comprising providing a quantum well for electrons via the second semiconductor layer.
4. The method of claim 1 , further comprising forming the first semiconductor layer comprising a compressive strained quantum well layer.
5. The method of claim 1 , further comprising forming the silicon on insulator core of pure silicon.
6. The method of claim 1 , further comprising forming the second semiconductor layer including a smaller bandgap than the bandgap of the semiconductor fin and a larger bandgap than the bandgap of the first semiconductor layer.
7. The method of claim 1 , further comprising forming the first semiconductor layer by growing the first semiconductor layer.
8. A method comprising:
forming a buried oxide layer directly on a substrate;
depositing a silicon layer directly over the buried oxide layer;
patterning the silicon layer to form a semiconductor fin comprising a silicon on insulator core directly on the buried oxide layer, the semiconductor fin providing a channel region for a non-planar transistor;
forming a first semiconductor layer comprising silicon germanium (SiGe) directly on and wrapped around the semiconductor fin and directly contacting at least a portion of the buried oxide layer, wherein the first semiconductor layer comprises a compressive strained quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin;
forming a second semiconductor layer comprising tensile strained silicon directly around the first semiconductor layer; and
forming a gate stack over the second semiconductor layer and directly contacting at least a portion of the buried oxide layer, the gate stack including a dielectric layer and a gate electrode.
9. The method of claim 8 , further comprising forming the first semiconductor layer having a Ge concentration of at least approximately 10%.
10. The method of claim 8 , further comprising providing a quantum well for holes via the first semiconductor layer.
11. The method of claim 10 , further comprising providing a quantum well for electrons via the second semiconductor layer.
12. A method comprising:
forming a buried oxide layer directly on a substrate;
forming a semiconductor fin comprising a silicon on insulator core directly on the buried oxide layer such that at least a portion of the buried oxide layer is interposed between the semiconductor fin and the substrate, the semiconductor fin providing a channel region for a non-planar transistor;
forming a first semiconductor layer comprising silicon germanium (SiGe) directly on and wrapped around the semiconductor fin and directly contacting at least a portion of the buried oxide layer, wherein the first semiconductor layer comprises a quantum well layer including a smaller bandgap than a bandgap of the semiconductor fin;
forming a second semiconductor layer comprising tensile strained silicon directly around the first semiconductor layer;
forming a dielectric layer adjacent the second semiconductor layer; and
forming a gate electrode adjacent the dielectric layer, the gate electrode and the dielectric layer directly contacting at least a portion of the buried oxide layer.
13. The method of claim 12 , further comprising forming the first semiconductor layer having a Ge concentration of at least approximately 10%.
14. The method of claim 12 , further comprising providing a quantum well for holes via the first semiconductor layer.
15. The method of claim 14 , further comprising providing a quantum well for electrons via the second semiconductor layer.