Transistor gate electrode having conductor material layer
View Patent ↗Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
1. A method comprising:
in a circuit substrate, forming a transistor device channel comprising a layer of silicon germanium (SiGe) material; and
forming a gate electrode for the transistor device, the gate electrode comprising a conductor material, and a layer of semiconductor material over the conductor material, wherein the conductor material is one of a titanium nitride (TiN), a tantalum nitride (TaN), and a silicide, wherein forming the gate electrode further includes:
one of flowing during forming with or doping after forming the layer of semiconductor material with one of boron and aluminum to form a P-type gate electrode having an electrically positive charge.
2. The method of claim 1 , wherein forming the channel includes depositing a sufficient thickness of a silicon germanium material to cause a compressive strain in the channel caused by a difference in lattice spacing of the circuit substrate material and a lattice spacing of at least one junction region proximate to the SiGe material causing a hydrostatic pressure on the SiGe material.
3. The method of claim 1 , wherein forming the channel includes depositing a sufficient thickness of a silicon germanium material to cause a bi-axial compressive strain in the channel caused by a lattice spacing of the SiGe material being larger than a lattice spacing of a substrate material defining an interface surface of the substrate.
4. The method of claim 3 , wherein forming the channel includes
selective chemical vapor deposition (CVD) epitaxial growth of a layer of compressive strained SiGe material having a thickness of between 20 nanometers and 30 nanometers in thickness on a substrate having a thickness of between 1 and 3 micrometers in thickness.
5. The method of claim 3 , wherein forming the channel comprises:
depositing a layer of SiGe material by a blanket deposition process;
forming an electronically insulating material in the channel material and the substrate between the interface surface and a surrounding region, after depositing the layer of SiGe material.
6. The method of claim 1 , wherein the conductor material has a work function between 4.4 electron Volts and 4.7 electron Volts with respect to silicon.
7. The method of claim 1 , wherein forming a gate electrode includes depositing a thickness of between 10 angstroms and 20 angstroms in thickness of the conductor material by one of an physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a Chemical vapor deposition (CVD) process.
8. The method of claim 1 , further comprising:
forming a gate dielectric between the channel and the gate electrode, the gate dielectric comprising a gate dielectric material having a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ).
9. The method of claim 8 , wherein the gate dielectric material is one of silicon dioxide (SiO 2 ), hafnium oxide (HfO), hafnium silicate (HfSiO 4 ), hafnium disilicate (HfSi 4 O 7 ), zirconium oxide (ZrO), zirconium silicate (ZrSiO 4 ), tantalum oxide (Ta 2 O 5 ).
10. The method of claim 8 , wherein forming a gate electrode includes depositing a sufficient thickness of the conductor material to relieve electron depletion effects at an interface between the gate electrode and the gate dielectric.