Tri-gate transistors and methods to fabricate same
View Patent ↗Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.
1. A method comprising:
disposing a trench layer upon a semiconductor substrate;
forming one or more trenches in the trench layer exposing the semiconductor substrate;
epitaxially growing a semiconductor material within the one or more trenches to fill the one or more trenches; and
removing a portion of the trench layer to expose the semiconductor material as one or more semiconductor fins.
2. The method of claim 1 wherein the trench layer is comprised of a plurality of layers.
3. The method of claim 2 wherein the plurality of layers include a first oxide layer disposed upon the semiconductor substrate, a nitride layer disposed upon the first oxide layer, and a second oxide layer disposed upon the nitride layer.
4. The method of claim 3 wherein removing a portion of the trench layer comprises removing any remaining portion of the second oxide layer, any remaining portion of the nitride layer, and retaining at least some portion of any remaining portion of the first oxide layer.
5. The method of claim 1 wherein the one or more trenches have a depth of approximately 10 nm.
6. The method of claim 5 wherein the one or more semiconductor fins have a height of approximately 10 nm that is uniform to within 5%.
7. The method of claim 1 , further comprising:
planarizing the semiconductor material to a surface of the trench layer prior to exposing the semiconductor material as one or more semiconductor fins.
8. The method of claim 1 wherein filling the one or more trenches with a semiconductor material includes a blanket deposition of semiconductor material.
9. A method comprising:
disposing a first oxide layer on a semiconductor substrate;
disposing a nitride layer upon the first oxide layer;
disposing a second oxide layer upon the nitride layer;
selectively etching a portion of the second oxide layer, the nitride layer and the first oxide layer to define one or more trenches;
epitaxially growing a semiconductor material within the one or more trenches to fill the one or more trenches; and
selectively etching a remainder of the second oxide layer to form one or more semiconductor bodies from the semiconductor material.
10. The method of claim 9 wherein the one or more trenches have a depth of approximately 10 nm.
11. The method of claim 9 wherein the one or more semiconductor bodies have a height of less than 20 nm that is uniform to within 5%.
12. The method of claim 11 wherein the one or more semiconductor bodies have a height of approximately 10 nm.
13. The method of claim 9 further comprising:
planarizing the semiconductor material to a surface of the second oxide layer.
14. The method of claim 9 wherein the semiconductor substrate is comprised of a semiconductor material selected from the group consisting of silicon, germanium, and gallium arsenide.
15. The method of claim 9 wherein the semiconductor substrate is comprised of silicon, the first oxide layer is comprised of SiO 2 , the nitride layer is comprised of Si 3 N 4 , and the second oxide layer is comprised of SiO 2 .
16. A method comprising:
forming a first film over a semiconductor substrate;
forming a second film on said first film;
forming a trench in said first film and said second film and exposing the semiconductor substrate;
forming an epitaxial semiconductor film in said trench; and
exposing a sidewall of said semiconductor film by removing said second film selectively from said first film.
17. The method in claim 16 , further comprising:
forming a gate dielectric on said sidewall of said semiconductor film;
forming a gate electrode on said gate dielectric; and
forming a source and drain region in said semiconductor film on opposite sides of said gate electrode.
18. The method in claim 16 , wherein said first film is a silicon nitride and said second film is a silicon oxide.
19. The method in claim 16 , wherein said first film is a silicon oxide and said second film is a silicon nitride.
20. The method in claim 16 , further comprising:
removing any excess semiconductor material from said trench prior to exposing a sidewall of said semiconductor film.