Detecting architectural vulnerability of processor resources
View Patent ↗In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
1. An apparatus comprising:
a plurality of counters to maintain utilization values, each for a storage unit of a processor during a quantum;
a second counter to count a number of mispredictions made by a prediction unit of the processor during the quantum; and
a first logic to determine a vulnerability measure for at least a first portion of the processor for the quantum based at least in part on the utilization values and the number of mispredictions.
2. The apparatus of claim 1 , further comprising a second logic to determine a vulnerability measure for a second portion of the processor for the quantum based at least in part on a second set of utilization values and the number of mispredictions.
3. The apparatus of claim 2 , wherein the at least the first portion of the processor corresponds to a front end unit of the processor, and the second portion of the processor corresponds to a back end unit of the processor.
4. The apparatus of claim 1 , wherein the first logic is to receive the utilization values and to determine the vulnerability measure according to a linear function having a plurality of terms each including a coefficient and one of the utilization values.
5. The apparatus of claim 4 , further comprising a second logic to receive the vulnerability measure and to generate a control signal to control at least one error mitigation unit of the processor based on the vulnerability measure.
6. The apparatus of claim 5 , wherein the second logic is to enable an error detection mechanism of the at least one error mitigation unit if the vulnerability measure is greater than a first threshold and is to enable an error correction mechanism of the at least one error mitigation unit if the vulnerability measure is greater than a second threshold.
7. The apparatus of claim 5 , wherein the second logic is to receive a plurality of vulnerability measures each for one of a plurality of quanta and is to generate the control signal based on the plurality of vulnerability measures.
8. The apparatus of claim 5 , wherein the second logic is to disable the at least one error mitigation unit if the vulnerability measure is less than the first threshold, and wherein the at least one error mitigation unit is to be configured to perform non-error mitigation tasks when disabled by the second logic.
9. The apparatus of claim 5 , wherein the second logic is to dynamically control the at least one error mitigation unit to be enabled during a first portion of a program based on vulnerability measures of a first plurality of quanta and to be disabled based on vulnerability measures of a second plurality of quanta.
10. The apparatus of claim 1 , wherein the apparatus comprises the processor and further comprising a detector including the plurality of counters, the second counter and the first logic, wherein the detector is associated with the first portion of the processor.
11. The apparatus of claim 10 , wherein at least one of the plurality of counters of the detector is associated with a structure in a second portion of the processor.
12. A method comprising:
determining a quantized-architectural vulnerability factor (Q-AVF) value for a quantum for at least a portion of a processor using processor metric values, each corresponding to a utilization value for one of a plurality of front end structures of the processor;
comparing the Q-AVF value to at least one threshold value; and
dynamically controlling at least one error mitigation unit of the processor based on the comparison.
13. The method of claim 12 , further comprising determining the Q-AVF value according to a linear equation having a plurality of terms each corresponding to a processor metric value and a weight value.
14. The method of claim 12 , wherein a first utilization value corresponds to a number of valid entries in a structure for each cycle of the quantum.
15. The method of claim 14 , further comprising determining the first utilization value via shifting the number of valid entries by a logarithmic value corresponding to the quantum.
16. The method of claim 12 , further comprising determining the Q-AVF value for a front end unit of the processor based on processor metric values for an instruction decode queue of the front end unit, a branch predictor of the front end unit, and a retirement order buffer of a back end unit of the processor.
17. A system comprising:
a multicore processor having a plurality of cores, wherein a first core includes a detector to detect a vulnerability measure for the first core based on a plurality of processor metric values each associated with operation of a core structure during a first time period, and a controller to control an error mitigation unit of the first core based on the vulnerability measure, to enable an error detection mechanism of the error mitigation unit if the vulnerability measure is greater than a first threshold, and to enable an error correction mechanism of the error mitigation unit if the vulnerability measure is greater than a second threshold; and
a dynamic random access memory (DRAM) coupled to the multicore processor.
18. The system of claim 17 , wherein the detector includes a plurality of counters each to maintain the processor metric values during the first time period, a second counter to count a number of mispredictions made by a prediction unit of the first core during the first time period, and a first logic to determine the vulnerability measure for at least a first portion of the first core for the first time period based at least in part on the processor metric values and the number of mispredictions.
19. The system of claim 18 , wherein the detector further comprises a second logic to determine a second vulnerability measure for a second portion of the first core for the first time period based at least in part on a second set of processor metric values and the number of mispredictions.
20. The system of claim 18 , wherein the first logic is to receive the processor metric values and to determine the vulnerability measure according to a linear function having a plurality of terms each including a coefficient and one of the processor metric values.
21. The system of claim 17 , wherein the controller is to receive a plurality of vulnerability measures each for one of a plurality of time periods and is to generate a control signal based on the plurality of vulnerability measures.
22. The system of claim 17 , wherein the error mitigation unit is to be configured to perform non-error mitigation tasks when disabled by the controller.