Methods of containing defects for non-silicon device engineering
An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.
1. An apparatus comprising:
a semiconductor device comprising a channel material having a first lattice structure on a well of a well material having a matched lattice structure, the well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, wherein the well comprises an aspect ratio of height to width and height to length each greater than 1.5.
2. The apparatus of claim 1 , wherein the semiconductor device comprises an n-type metal oxide semiconductor field effect transistor comprising a source region and a drain region of the channel material.
3. The apparatus of claim 1 , wherein the channel material is a Group III-V compound semiconductor material.
4. The apparatus of claim 3 , wherein the buffer material comprises Germanium.
5. The apparatus of claim 1 , wherein the semiconductor device is a first semiconductor device comprising an n-type metal oxide semiconductor field effect transistor, the apparatus further comprising a second semiconductor device comprising a p-type metal oxide semiconductor field effect transistor form on the buffer material.
6. The apparatus of claim 5 , wherein the n-type transistor is connected to the p-type transistor through the gates and drains of each device.
7. A method comprising:
forming a well trench in a buffer material of a substrate the well having an aspect ratio of height to width and height to length greater than 1.5;
forming an n-type well material in the well trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material;
defining an area for a channel and for junction regions for an n-type device on the well material; and
forming an n-type transistor comprising a channel and junction regions in the defined area.
8. The method of claim 7 , wherein the area for a channel and junction regions is defined by trench isolation.
9. The method of claim 7 , wherein the n-type well material is a Group III-V compound semiconductor material.
10. The method of claim 9 , wherein the buffer material comprises Germanium.
11. The method of claim 7 , further comprising:
defining a p-type area for a channel and for junction regions for a p-type device on the well material; and
forming a p-type transistor comprising a channel and junction regions in the defined p-type area.
12. The method of claim 11 , wherein the n-type transistor comprises a gate and the p-type transistor comprises a gate, and the junction regions of each transistor comprise a source region and a drain region, the method further comprising:
connecting the n-type transistor to the p-type transistor through the gates and drains of each device.
13. The system of claim 12 , wherein the channel material of the n-type transistor is a Group III-V compound semiconductor material.
14. The system of the claim 12 , wherein the buffer material comprises Germanium.
15. A system comprising:
a computer comprising a processor electrically coupled to a printed circuit board, the processor comprising complimentary metal oxide semiconductor (CMOS) circuitry including an n-type transistor and a p-type transistor, the n-type transistor comprising a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, wherein the well comprises an aspect ratio of height to width and height to length each greater than 1.5, wherein the n-type transistor is coupled to the p-type transistor through a gate and a drain of each device.