Determining demarcation voltage via timestamps
In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.
1. A method comprising,
in response to a write operation on a storage element in a non-volatile memory device, storing a time at which the write operation occurs on the storage element; and
in response to receiving a request to perform a read operation on the storage element, determining a demarcation voltage to apply for performing the read operation on the storage element, wherein:
the demarcation voltage is a first voltage if a time duration between the read operation on the storage element and the write operation on the storage element is relatively small; and
the demarcation voltage is a second voltage that is greater than the first voltage if the time duration between the read operation on the storage element and the write operation on the storage element is relatively large.
2. The method of claim 1 , wherein the storage element is a sub-block of a block.
3. The method of claim 2 , wherein the non-volatile memory device is comprised of a plurality of non-volatile memory cells that comprise the block, wherein the block is comprised of a plurality of sub-blocks, and wherein each sub-block is separately addressable for reading or writing.
4. The method of claim 2 , wherein the time at which the write operation occurs on the sub-block is indicated by storing a count provided by a global counter, and wherein the demarcation voltage to apply for performing the read operation on the storage element is based on a progress of the global counter since the write operation on the storage element.
5. The method of claim 2 , wherein for each sub-block, a plurality of bits that are equal in number to a number of bits of a global counter is maintained for storing a count provided by the global counter to indicate the time at which the write operation occurs on the sub-block of the block.
6. A method comprising,
in response to a write operation on a sub-block of a block in a non-volatile memory device, storing a count provided by a global counter to indicate a time at which the write operation occurs on the sub-block; and
in response to receiving a request to perform a read operation on the sub-block, determining a demarcation voltage to apply for performing the read operation on the sub-block, based on a progress of the global counter since the write operation on the sub-block, wherein the progress of the global counter since the write operation on the sub-block is determined by maintaining for the block a plurality of bits that are equal in number to a number of bits of the global counter, and a local counter for each sub-block, and wherein the number of bits of the local counter is less than the number of bits of the global counter.
7. The method of claim 6 , wherein the local counter indicates a time difference relative to a count stored in the plurality of bits that are equal in number to a number of bits of the global counter.
8. The method of claim 7 , wherein the local counter for the sub-block in combination with the count stored in the plurality of bits indicates a time at which the write operation occurs on the sub-block.
9. A non-volatile memory device, comprising:
a non-volatile memory; and
a controller coupled to the non-volatile memory, wherein the controller is operable to:
in response to a write operation on a storage element, store a time at which the write operation occurs on the storage element; and
in response to receiving a request IQ perform a read operation on the storage element, determine a demarcation voltage to apply for performing the read operation on the storage element, wherein:
the demarcation voltage is a first voltage if a time duration between the read operation on the storage element and the write operation on the storage element is relatively small; and
the demarcation voltage is a second voltage that is greater than the first voltage if the time duration between the read operation on the storage element and the write operation on the storage element is relatively large.
10. The non-volatile memory device of claim 9 , wherein the storage element is a sub-block of a block.
11. The non-volatile memory device of claim 10 , wherein the non-volatile memory device is comprised of a plurality of non-volatile memory cells that comprise the block, wherein the block is comprised of a plurality of sub-blocks, and wherein each sub-block is separately addressable for reading or writing.
12. The non-volatile memory device of claim 10 , wherein the time at which the write operation occurs on the sub-block is indicated by storing a count provided by a global counter, and wherein the demarcation voltage to apply for performing the read operation on the storage element is based on a progress of the global counter since the write operation on the storage element.
13. The non-volatile memory device of claim 10 , wherein for each sub-block, a plurality of bits that are equal in number to a number of bits of a global counter is maintained for storing a count provided by the global counter to indicate the time at which the write operation occurs on the sub-block of the block.
14. A non-volatile memory device, comprising:
a non-volatile memory; and
a controller coupled to the non-volatile memory, wherein the controller is operable to:
in response to a write operation on a sub-block of a block in a non-volatile memory device, store a count provided by a global counter to indicate a time at which the write operation occurs on the sub-block; and
in response to receiving a request to perform a read operation on the sub-block, determine a demarcation voltage to apply for performing the read operation on the sub-block, based on a progress of the global counter since the write operation on the sub-block wherein the progress of the global counter since the write operation on the sub-block is determined by maintaining for the block a plurality of bits that are equal in number to a number of bits of the global counter, and a local counter for each sub-block, and wherein the number of bits of the local counter is less than the number of bits of the global counter.
15. The non-volatile memory device of claim 14 , wherein the local counter indicates a time difference relative to a count stored in the plurality of bits that are equal in number to a number of bits of the global counter.
16. The non-volatile memory device of claim 15 , wherein the local counter for the sub-block in combination with the count stored in the plurality of bits indicates a time at which the write operation occurs on the sub-block.
17. A system, comprising:
a display;
a non-volatile memory device comprised of a non-volatile memory; and
a controller that controls the non-volatile memory, wherein the controller is operable to:
in response to a write operation on a storage element, store a time at which the write operation occurs on the storage element; and
in response to receiving a request to perform a read operation on the storage element, determine a demarcation voltage to apply for performing the read operation on the storage element, wherein:
the demarcation voltage is a first voltage if a time duration between the read operation on the storage element and the write operation on the storage element is relatively small; and
the demarcation voltage is a second voltage that is greater than the first voltage if the time duration between the read operation on the storage element and the write operation on the storage element is relatively large.
18. The system of claim 17 , wherein the storage element is a sub-block of a block.
19. The system of claim 18 , wherein the non-volatile memory device is comprised of a plurality of non-volatile memory cells that comprise the block, wherein the block is comprised of a plurality of sub-blocks, and wherein each sub-block is separately addressable for reading or writing.
20. The system of claim 18 , wherein the time at which the write operation occurs on the sub-block is indicated by storing a count provided by a global counter, and wherein the demarcation voltage to apply for performing the read operation on the storage element is based on a progress of the global counter since the write operation on the storage element.
21. The system of claim 18 , wherein for each sub-block, a plurality of bits that are equal in number to a number of bits of a global counter is maintained for storing a count provided by the global counter to indicate the time at which the write operation occurs on the sub-block of the block.
22. A system, comprising:
a display;
a non-volatile memory device comprised of a non-volatile memory; and
a controller that controls the non-volatile memory, wherein the controller is operable to:
in response to a write operation on a sub-block of a block in a non-volatile memory device, store a count provided by a global counter to indicate a time at which the write operation occurs on the sub-block; and
in response to receiving a request to perform a read operation on the sub-block, determine a demarcation voltage to apply for performing the read operation on the sub-block, based on a progress of the global counter since the write operation on the sub-block, wherein the progress of the global counter since the write operation on the sub-block is determined by maintaining for the block a plurality of bits that are equal in number to a number of bits of the global counter, and a local counter for each sub-block, and wherein the number of bits of the local counter is less than the number of bits of the global counter.
23. The system of claim 22 , wherein the local counter indicates a time difference relative to a count stored in the plurality of bits that are equal in number to a number of bits of the global counter.
24. The system of claim 23 , wherein the local counter for the sub-block in combination with the count stored in the plurality of bits indicates a time at which the write operation occurs on the sub-block.