IP Library Granted Patent US 8,171,231
Granted Patent B2
US 8,171,231 · App. 13/207,318 · Granted May 1, 2012

System and method for aggregating core-cache clusters in order to produce multi-core processors

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Quick Facts
Patent No.
US 8,171,231
App. No.
13/207,318
Granted
May 1, 2012
Kind
B2
Abstract

According to one embodiment of the invention, a processor comprises a memory, a plurality of core-cache clusters and a scalability agent unit that operates as an interface between an on-die interconnect and multiple core-cache clusters. The scalability agent operates in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent.

Claims (30)

1. A method comprising:

providing a plurality of core-cache clusters, each of the plurality of core-cache clusters including a cache memory and at least one processor core in communication with the cache memory; and

operating in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent.

2. The method of claim 1 , wherein the operating in accordance with a protocol comprises controlling, by at least one scalability agent, all coherent transactions issued by the plurality of core-cache clusters.

3. The method of claim 2 , wherein the at least one scalability agent issues snoop requests to core-cache clusters of the plurality of core-cache clusters while concurrently issuing a transaction to a system interconnect.

4. The method of claim 3 , wherein the at least one scalability agent collects snoop responses from the core-cache clusters.

5. The method of claim 4 , wherein the at least one scalability agent issues an aggregate response to a requesting core-cache cluster of the plurality of core-cache clusters.

6. The method of claim 4 , wherein the at least one scalability agent performs address checking operations in order to ensure that only one transaction for a given address can be issued to the system interconnect.

7. The method of claim 2 , wherein the at least one scalability agent issues snoop requests to the plurality of core-cache clusters and collects snoop responses from all of the plurality of core-cache clusters.

8. The method of claim 7 , wherein the at least one scalability agent sends a single snoop response to a requesting socket.

9. The method of claim 1 , wherein the scalability agent includes a plurality of scalability agent units each uniquely corresponding to a core-cache cluster of the plurality of core-cache clusters and responsible for a subset of an address space.

10. A method comprising:

configuring a multi-core processor with a plurality of core-cache clusters, each core-cache cluster including at least one processor core and a scalability agent unit to manage a flow of information with the plurality of core-cache clusters; and

coupling the multi-core processor to a system interconnect, the plurality of core-cache clusters to appear as a single caching agent to devices communicatively coupled to the system interconnect.

11. The method of claim 10 further comprising:

handling local coherence between the plurality of core-cache clusters by each scalability agent unit issuing snoops and collecting responses to check for address conflicts.

12. The method of claim 11 , wherein each of the plurality of scalability agent units is further adapted to send a snoop response message aggregated from the collected snoop responses over the system interconnect so that the plurality of core-cache clusters appear as the single caching agent.

13. The method of claim 11 , wherein each scalability agent unit is responsible for a different portion of a system memory address space.

14. The method of claim 11 , wherein the configuring of the multi-core processor further comprises configuring each scalability agent to handle an equal amount of work.

15. A system comprising:

a memory; and

a processor coupled to the memory, the processor comprises:

an on-die interconnect,

a plurality of core-cache clusters, each of the plurality of core-cache clusters including both a cache memory and one or more processor cores in communication with the cache memory, and

a scalability agent coupled to the on-die interconnect, the scalability agent operating in accordance with a protocol to ensure that the plurality of core-cache clusters appear as a single caching agent.

16. The system of claim 15 , wherein the scalability agent of the processor includes a plurality of scalability agent units each uniquely associated with one of the plurality of core-cache clusters and adapted to issue a snoop message and collect snoop responses to the snoop message.

17. The system of claim 16 , wherein each of the plurality of scalability agent units of the processor is further adapted to send a snoop response message aggregated from the collected snoop responses over a system interconnect so that the plurality of core-cache clusters appear as the single caching agent.

18. The system of claim 16 , wherein the plurality of scalability agent units of the processor correspond in number to the plurality of core-cache clusters and each of the plurality of scalability agent units.

19. The system of claim 15 , wherein the plurality of core-cache clusters of the processor comprises a first core-cache cluster including (i) a first cache memory, (ii) a first plurality of processor cores in communication with the first cache memory, and (iii) a first scalability agent unit coupled to the on-die interconnect and in communication with the first cache memory and the first plurality of processor cores, the first scalability agent being responsible for a first portion of a system memory.

20. The system of claim 19 wherein the plurality of core-cache clusters of the processor further comprises a second core-cache cluster including (i) a second cache memory, (ii) a second plurality of processor cores in communication with the second cache memory, and (iii) a second scalability agent unit coupled to the on-die interconnect and in communication with the second cache memory and the second plurality of processor cores, the second scalability agent being responsible for a second portion of the system memory differing from the first portion of the system memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →