Method and apparatus for a zero voltage processor sleep state

1. A method comprising:

transitioning to a zero voltage power management state, wherein an operational voltage applied to a processor is reduced to approximately zero volts, the processor includes at least a first core and a second core;

saving state variables of the processor to a dedicated cache memory that is to remain powered while the operational voltage applied to the processor is reduced to approximately zero, the saving of the state variables of the processor include saving both a state of the first core and a state of the second core when the processor transitions to the zero voltage power management state for synchronizing restoration of the state of the first core and the state of the second core; and

exiting the zero voltage power management state at an operating voltage applied to the processor higher than the approximately zero volts.

2. The method of claim 1 , further comprising restoring the state variables of the processor after exiting the zero voltage power management state.

3. The method of claim 1 , further comprising monitoring a current voltage level during the transition to the zero voltage power management state.

4. The method of claim 3 , wherein monitoring the current voltage level further comprises:

determining the current voltage level of the processor using an analog to digital converter (ADC);

providing a digital voltage identification (VLD) representation based on the determined current voltage level to a voltage regulator, the voltage regulator providing the operating voltage to the processor; and

determining whether the current voltage level is higher than the operating voltage by comparing respective VIDs.

5. An apparatus comprising:

a processor including at least a first core, a second core, and a dedicated cache memory associated with the processor, the first core having a first unique identifier and the second core having a second unique identifier and the dedicated cache memory to restore the state variables of a particular core based on the unique identifier of that particular core; and

a voltage regulator coupled to the processor to provide an operating voltage to the processor;

wherein, the voltage regulator is to reduce the operational voltage applied to the processor to approximately zero volts during a transition to a zero voltage power management state for the processor, and after exiting the zero voltage power management state, the voltage regulator is to increase the operating voltage applied to the processor to an operating voltage state by supplying a voltage higher than the approximately zero volts and the operating state of the processor is restored from the dedicated cache memory, and

wherein the dedicated cache memory is to (i) receive state variables associated with the processor, (ii) restore the state variables of a particular core of the based on the unique identifier of that particular core, and (iii) remain powered while the operational voltage applied to the processor is reduced to approximately zero.

6. The apparatus of claim 5 , wherein the dedicated cache memory is a synchronous random access memory (SRAM) internal to a package containing the processor.

7. The apparatus of claim 5 , wherein the dedicated cache memory is to restore state variables to the core that was the last core to store its state variables in the dedicated cache memory.

8. A machine-readable storage medium having stored thereon instructions, which when executed by a machine including a processor, cause the machine to perform the following operations comprising:

transitioning to a zero voltage power management state, wherein an applied operational voltage is reduced to approximately zero;

saving state variables to a dedicated cache memory that is to remain powered while the operational voltage is reduced to approximately zero, the state variables include a state variable of a first core of the processor and a state variable of a second core of the processor;

exiting the zero voltage power management state at a higher operating voltage; and

restoring the state variables from the cache memory after exiting the zero voltage power management state.

9. The machine-readable storage medium of claim 8 , wherein the cache memory is a synchronous random access memory (SRAM).

10. The machine-readable storage medium of claim 8 , further comprising instructions to monitor a current voltage level during the transition to the zero voltage power management state.