Forming a non-planar transistor having a quantum well channel
View Patent ↗In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
1. A method comprising:
forming a buried oxide layer directly on a substrate;
forming a non-planar silicon on insulator (SOI) core directly on the buried oxide layer, the non-planar SOI core formed of a silicon fin on the buried oxide layer;
forming a quantum well (QW) layer directly around the non-planar SOI core, wherein the QW layer is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%, wherein the QW layer is compressive strained and having a smaller bandgap than the SOI core;
forming a silicon layer around the QW layer; and
the silicon layer having a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
2. The method of claim 1 , further comprising:
forming a gate dielectric layer over the silicon layer; and
forming a gate electrode layer over the gate dielectric layer.
3. The method of claim 1 , further comprising forming a non-planar transistor, wherein the quantum well layer comprises a channel of the non-planar transistor.
4. The method of claim 1 , further comprising forming a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT).
5. The method of claim 1 , further comprising forming the silicon fin having a width much less than a width of the buried oxide layer.
6. The method of claim 1 , wherein the non-planar SOI core is strained.
7. The method of claim 1 , wherein the silicon layer is tensile strained.
8. The method of claim 1 , wherein forming the QW layer includes depositing the QW layer directly on the non-planar SOI core and at least a portion of the buried oxide layer not including the silicon fin.
9. A method comprising:
forming a buried oxide layer including silicon dioxide directly on a substrate;
forming a non-planar silicon on insulator (SOI) core directly on the buried oxide layer, the non-planar SOI core formed of a silicon fin on the buried oxide layer having a width much less than an extent of the buried oxide layer;
forming a quantum well (QW) layer directly around the non-planar SOI core, wherein the QW layer is formed of silicon germanium (SiGe) having a Ge concentration of at least approximately 10%, wherein the QW layer is compressive strained and having a smaller bandgap than the non-planar SOI core;
forming a silicon layer around the QW layer; and
the silicon layer having a smaller bandgap than the SOI core and a larger bandgap than the QW layer.
10. The method of claim 9 , further comprising:
forming a gate dielectric layer over the silicon layer; and
forming a gate electrode layer over the gate dielectric layer.
11. The method of claim 9 , further comprising forming a non-planar transistor, wherein the quantum well layer comprises a channel of the non-planar transistor.
12. The method of claim 9 , further comprising forming a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT).
13. The method of claim 9 , wherein forming the QW layer includes vapor deposition.
14. The method of claim 9 , wherein forming the silicon layer includes vapor deposition.