Apparatus, system, and method for persistent user-level thread

1. A processor comprising:

a first hardware core comprising at least one operating-system-visible sequencer to execute instructions scheduled by an operating system; and

a second hardware core comprising at least one operating-system-sequestered sequencer for which the operating system does not schedule instructions, wherein the at least one operating-system-visible sequencer is to create a persistent user-level thread to run on the at least one operating-system-sequestered sequencer, wherein the persistent user-level thread is to continue execution, irrespective of context switch activities of an operating-system-scheduled thread executed on the at least one operating-system-visible sequencer.

2. The processor of claim 1 , wherein the processor is to suspend execution of the persistent user-level thread when the persistent user-level thread encounters an event to be handled by the operating system, and to communicate to a second operating-system-visible sequencer a control-transfer instruction for execution at a privileged level.

3. The processor of claim 2 , further comprising a sequencer manager to cause a service thread executed on the at least one operating-system-visible sequencer to imitate the suspended persistent user-level thread to provide operating system services to the suspended persistent user-level thread.

4. The processor of claim 3 , wherein the sequencer manager is to:

cause the service thread to pick up a state of the persistent user-level thread via the imitation;

provide a proxy execution to the persistent user-level thread; and

return a post execution state to the persistent user-level thread to enable the persistent user-level thread to resume running from the post execution state.

5. The processor of claim 1 , further comprising a plurality of hardware cores.

6. The processor of claim 5 , wherein at least one of the plurality of hardware cores is asymmetric to another of the plurality of hardware cores.

7. The processor of claim 5 , wherein a first portion of the plurality of hardware cores are visible to the operating system and a second portion of the plurality of cores are invisible to the operating system.

8. The processor of claim 1 , wherein the processor comprises a digital signal processor (DSP).

9. The processor of claim 1 , wherein the second hardware core is adapted to process a subset of instructions of an instruction set architecture (ISA).

10. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

creating a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on an operating-system-scheduled thread running on an operating-system-visible sequencer, wherein the persistent user-level thread continues execution when the operating-system-scheduled thread is context switched;

suspending running of the persistent user-level thread when the persistent user-level thread encounters an event to be handled by an operating system; and

communicating to another operating-system-visible sequencer a control-transfer instruction, and executing the control-transfer instruction at a privileged level.

11. The non-transitory machine-readable medium of claim 10 , wherein the operating-system-scheduled thread and the persistent user-level thread share a common virtual address space.

12. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises causing a service thread running on another operating-system-visible sequencer to imitate the suspended persistent user-level thread to provide operating system services to the suspended persistent user-level thread, the imitating enabling the service thread to access an execution state of the suspended persistent user-level thread.

13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises:

causing the service thread to access the execution state of the persistent user-level thread through a common shared virtual address space;

providing a proxy execution to the persistent user-level thread; and

returning a post execution state to the persistent user-level thread.

14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises resuming running of the persistent user-level thread from the post execution state.

15. The non-transitory machine-readable medium of claim 13 , wherein the service thread and the persistent user-level thread run in the context of a same application.

16. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises processing instructions at a first rate in the operating-system-visible sequencer and at a second rate in the operating-system-sequestered sequencer.

17. A system comprising:

a multi-core processor including a plurality of cores and a controller to create a persistent user-level thread to run on an operating-system-sequestered core independently of context switch activities on an operating-system-scheduled thread to run on an operating-system-visible core, wherein the persistent user-level thread is to continue execution when the operating-system-scheduled thread is context switched, communicate a control-transfer instruction to another operating-system-visible core, and execute the control-transfer instruction at a privileged level; and

a dynamic random access memory (DRAM) coupled to the multi-core processor.

18. The system of claim 17 , wherein the persistent user-level thread is to be suspended when the persistent user-level thread encounters an event to be handled by an operating system, and a service thread to run on the another operating-system-visible core is to imitate the suspended persistent user-level thread to provide operating system services to the suspended persistent user-level thread.

19. The system of claim 18 , wherein the system is to:

cause the service thread to access an execution state of the persistent user-level thread through a common shared virtual address space;

provide a proxy execution to the persistent user-level thread; and

return a post execution state to the persistent user-level thread, wherein the persistent user-level thread is to resume from the post execution state.

20. The system of claim 17 , wherein the multi-core processor is to process instructions at a first rate in the operating-system-visible core and at a second rate in the operating-system-sequestered core.