IP Library Granted Patent US 8,039,920
Granted Patent B1
US 8,039,920 · App. 12/948,410 · Granted Oct 18, 2011

Methods for forming planarized hermetic barrier layers and structures formed thereby

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Quick Facts
Patent No.
US 8,039,920
App. No.
12/948,410
Granted
Oct 18, 2011
Kind
B1
Abstract

Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Claims (11)

1. A structure comprising:

a low density dielectric material disposed over patterned conductive material within a first low k ILD disposed on a substrate;

a high density dielectric barrier material disposed on the low density dielectric material, wherein the high density dielectric material comprises a thickness less than about ¼ of a thickness of the low density material; and

a second ILD disposed on the high density dielectric barrier material.

2. The structure of claim 1 wherein the high density dielectric barrier material comprises at least one of SiC:H, SiCN:H, SiOC:H, SiNx:H, SiC:H, SiBN, BN, and AIN.

3. The structure of claim 1 wherein the conductive material comprises at least one of a dopant surface interface layer, a hydride surface interface layer, and a metal cap.

4. The structure of claim 1 wherein the high density dielectric barrier material comprises a density greater than about 2.2 g/cm 3 and a k value greater than about 4.0.

5. The structure of claim 1 wherein the high density dielectric barrier material comprises a thickness of about 1 nm to about 6 nm.

6. The structure of claim 1 wherein the high density dielectric barrier layer disposed on the low density barrier layer comprises a dual layer dielectric barrier layer.

7. The structure of claim 6 further comprising wherein the dual layer dielectric barrier comprises an hermetic barrier layer.

8. The structure of claim 1 wherein the low density dielectric material planarizes the underlying conductive material an ILD layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →