Method and apparatus for fast lock acquisition in self-biased phase locked loops

1. A self-biased phase locked loop (PLL) circuit to generate an output signal having a target frequency based upon a reference clock signal, the PLL comprising:

a charge pump to generate a control voltage;

a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage;

discharge circuitry coupled to the charge pump to discharge the control voltage; and

frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

2. The self-biased PLL of claim 1 , wherein the threshold frequency is programmably determinable.

3. The self-biased PLL of claim 1 , wherein the controlled oscillator comprises a voltage controlled oscillator.

4. The self-biased PLL of claim 1 , wherein the controlled oscillator comprises a current controlled oscillator.

5. The self-biased PLL of claim 1 , wherein the frequency detection circuitry comprises a plurality of flip-flops sequentially coupled together such that an input signal applied to an input terminal of a first flip flop is asynchronously output from an output terminal of a last flip flop.

6. The self-biased PLL of claim 5 , wherein a reference clock signal is coupled to a reset terminal on each of the plurality of flip flops and the output signal is coupled to a clock terminal on each of the plurality of flip flops.

7. The self-biased PLL of claim 6 , wherein the digital feedback signal is output from the last flip flop and is coupled to the discharge circuitry.

8. The self-biased PLL of claim 7 , wherein the digital feedback signal transitions from a first logic level to a second opposite logic level to facilitate termination of the control voltage discharge.

9. The self-biased PLL of claim 1 , further comprising:

bias circuitry coupled to the discharge circuitry and at least one of the charge pump and the controlled oscillator to generate an analog feedback signal to facilitate termination of the control voltage discharge prior to the target frequency being reached.

10. The self-biased PLL of claim 9 , further comprising:

a PFD coupled to the charge pump and the discharge circuitry to generate a control signal based upon one or more differences between a reference clock signal and a frequency divided feedback signal derived from the output signal, the control signal to facilitate termination of the control voltage discharge based upon a state of the control signal.

11. A system comprising:

a communication bus;

a DRAM coupled to the bus; and

an integrated circuit (IC) coupled to the DRAM via the bus, the IC having a self-biased phase locked loop (PLL) to generate an output signal having a target frequency based upon a reference clock signal, the self-biased PLL including

a charge pump to generate a control voltage;

a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage;

discharge circuitry coupled to the charge pump to discharge the control voltage; and

frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

12. The system according to claim 11 , wherein the integrated circuit further includes a central processing unit, a main memory coupled to the central processor unit and at least one input/output module coupled to the central processor unit and the main memory.

13. The system of claim 11 , wherein the integrated circuit is a microprocessor.

14. The system of claim 11 , further comprising a networking interface coupled to the bus.

15. The system of claim 11 , wherein the system is a selected one of a set-top box, an entertainment unit and a DVD player.

16. The self-biased PLL of claim 11 , wherein the threshold frequency is programmably determinable.

17. The self-biased PLL of claim 11 , wherein the frequency detection circuitry comprises a plurality of flip-flops sequentially coupled together such that an input signal applied to an input terminal of a first flip flop is asynchronously output from an output terminal of a last flip flop.

18. An integrated circuit comprising:

a microprocessor;

a communication bus;

a DRAM coupled to the bus; and

a self-biased phase locked loop (PLL) to generate an output signal having a target frequency based upon a reference clock signal, the self-biased PLL including

discharge circuitry coupled to the charge pump to discharge a control voltage; and

frequency detection circuitry coupled to the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

19. The self-biased PLL of claim 18 , wherein the threshold frequency is programmably determinable.

20. The self-biased PLL of claim 18 , further comprising:

a charge pump to generate the control voltage; and

a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage.