Adaptive digital phase locked loop

1. A chip comprising:

a Digital Phase Locked Loop (DPLL) with a controllable filter for varying loop bandwidth as the DPLL is in operation, the controllable filter to increase the loop bandwidth when identifying sufficiently increased phase error in a loop of the DPLL; and

a filter control unit to control the loop bandwidth through control of the controllable filter, the filter control unit having a phase interpreter to identify phase error.

2. The chip of claim 1 , wherein the DPLL is an all digital PLL.

3. The chip of claim 1 , wherein the controllable filter employs an in-loop linearization technique.

4. The chip of claim 1 , wherein the controllable filter is a digital filter characterized by five or more coefficients.

5. The chip of claim 4 , wherein three or more of the coefficients are controllably variable.

6. The chip of claim 1 , wherein the filter control unit to control filter coefficients of the controllable filter, the filter coefficients used for controlling the loop bandwidth.

7. The chip of claim 6 , wherein the filter control unit to control the filter coefficients for the loop bandwidth to be at a suitable low level for maintaining low jitter and but high enough to provide sufficient responsiveness for nominal phase noise conditions.

8. The chip of claim 1 , wherein the controllable filter has a dominant pole that is at least nine times greater than a dominant zero in the controllable filter.

9. The chip of claim 1 , wherein the phase interpreter to calculate the phase error by scaling a raw phase error value derived from the controllable filter.

10. The chip of claim 1 , wherein the filter control unit to apply a step function for controlling the loop bandwidth in response to changes in the phase error.

11. The chip of claim 1 , wherein the filter control unit to control the loop bandwidth to increase in response to intermittent increases in the phase error and then to go back to a normal low level.

12. The chip of claim 1 , wherein the controllable filter is a digital filter characterized by two or more coefficients.

13. A method comprising:

in a control unit of a digital phase locked loop (DPLL) having a filter to be controlled by the control unit, identifying a phase error in the DPLL by calculating the phase error from data from the filter;

controlling the filter for the DPLL to have a high bandwidth if the phase error is too high; and

controlling the filter for the DPLL to have a lower bandwidth if the phase error is not too high.

14. The method of claim 13 , wherein controlling the filter for a high bandwidth comprises adjusting coefficients for the filter to provide a bandwidth level that is proportional to the phase error.

15. The method of claim 13 , wherein controlling the filter includes updating filter coefficients using arithmetic logic calculations within the control unit.

16. A computing system comprising:

a processor having at least one digital phase locked loop (DPLL) comprising:

an adjustably controllable digital filter; and

a control unit to control bandwidth of the DPLL by controlling the adjustably controllable digital filter, the control unit having a phase interpreter to identify phase error.

17. The system of claim 16 , wherein the system comprises a display for information to be displayed to a user.

18. The system of claim 17 , wherein the processor and the display are part of a portable wireless device.

19. The system of claim 16 , wherein the adjustably controllable digital filter to be characterized by four or more coefficients.

20. The system of claim 19 , wherein at least two of the coefficients of the four or more coefficients are controlled by the control unit.

21. The system of claim 16 , wherein the control unit is operable to control the bandwidth to normally be at a sufficiently low level for acceptably low jitter and to be at a higher level in response to a sufficient phase error increase.