Etchstop layers and capacitors
View Patent ↗Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.
1. A semiconductor device comprising,
a substrate having at least one dielectric layer disposed on the substrate surface;
a first dielectric etchstop layer and a second dielectric etchstop layer disposed on the dielectric layer, wherein the second dielectric etchstop layer is disposed directly on the first dielectric etchstop layer; and
a well formed through the first and second dielectric etchstop layers and in the at least one dielectric layer, wherein the well comprises inwardly tapered sidewalls and a bottom, and a first layer of conducting material is disposed on the inwardly tapered sidewalls and bottom of the well, an insulating layer disposed on the first layer of conducting material, and a second layer of conducting material disposed on the insulating layer.
2. The semiconductor device of claim 1 , wherein the second dielectric etchstop layer has a density that is greater than the first dielectric etchstop layer and a density that is greater than 3 g/cm 3 .
3. The semiconductor device of claim 2 , wherein the density of the second dielectric etchstop layer is in the range of 4 to 10 g/cm 3 .
4. The semiconductor device of claim 1 , wherein the first layer of conducting material is recessed relative to the inwardly tapered sidewalls of the well.
5. The semiconductor device of claim 1 , wherein the substrate comprises at least two dielectric layers, the dielectric layers are separated by an etchstop layer, and the second dielectric layer comprises a metal-filled trench or via that makes electrical contact with the first layer of conducting material.
6. The semiconductor device of claim 5 , wherein the metal-filled trench or via is in electrical contact with a transistor structure.
7. The semiconductor device of claim 1 , wherein the first dielectric etchstop layer is comprised of a dielectric material that is comprised of at least 95% silicon, carbon, nitrogen, oxygen, or combinations thereof.
8. The semiconductor device of claim 1 , wherein the second dielectric etchstop layer is comprised of a transition metal oxide.
9. The semiconductor device of claim 1 , wherein the second dielectric etchstop layer is comprised of a material selected from the group consisting of ZnO, HfO 2 , Al 2 O 3 , and TiO x .
10. The semiconductor device of claim 1 , wherein the second dielectric etchstop layer is comprised of a high-k material.
11. A method of fabricating a semiconductor device, the method comprising,
forming at least one dielectric layer on a substrate surface;
forming a first dielectric etchstop layer and a second dielectric etchstop layer on the dielectric layer, wherein the second dielectric etchstop layer is formed directly on the first dielectric etchstop layer;
forming a well formed through the first and second dielectric etchstop layers and in the at least one dielectric layer, wherein the well comprises inwardly tapered sidewalls and a bottom;
forming a first layer of conducting material on the inwardly tapered sidewalls and bottom of the well
forming an insulating layer on the first layer of conducting material; and
forming a second layer of conducting material on the insulating layer.
12. The method of claim 11 , wherein the second dielectric etchstop layer has a density that is greater than the first dielectric etchstop layer and a density that is greater than 3 g/cm 3 .
13. The method of claim 12 , wherein the density of the second dielectric etchstop layer is in the range of 4 to 10 g/cm 3 .
14. The method of claim 11 , further comprising:
recessing the first layer of conducting material relative to the inwardly tapered sidewalls of the well.
15. The method of claim 11 , wherein the substrate comprises at least two dielectric layers, the dielectric layers are separated by an etchstop layer, and the second dielectric layer comprises a metal-filled trench or via that makes electrical contact with the first layer of conducting material.
16. The method of claim 15 , wherein the metal-filled trench or via is in electrical contact with a transistor structure.
17. The method of claim 11 , wherein the first dielectric etchstop layer is comprised of a dielectric material that is comprised of at least 95% silicon, carbon, nitrogen, oxygen, or combinations thereof.
18. The method of claim 11 , wherein the second dielectric etchstop layer is comprised of a transition metal oxide.
19. The method of claim 11 , wherein the second dielectric etchstop layer is comprised of a material selected from the group consisting of ZnO, HfO 2 , Al 2 O 3 , and TiO x .
20. The method of claim 11 , wherein the second dielectric etchstop layer is comprised of a high-k material.
21. The device of claim 17 wherein the second etchstop layer is comprised of a material selected from the group consisting of ZnO, HfO 2 , Al 2 O 3 , and TiO x .