Decoupled via fill
View Patent ↗Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.
1. An integrated circuit structure, comprising:
a dielectric layer;
a trench in the dielectric layer, the trench having a lower portion with sidewalls and an upper portion with sidewalls;
a first barrier layer along and in contact with the sidewalls of the lower portion of the trench, the first barrier layer having a first barrier layer composition;
a first fill material on the first barrier layer in the lower portion of the trench, the first fill material having a first fill material composition;
a second barrier layer along and in contact with the sidewalls of the upper portion of the trench, the second barrier layer having a second barrier layer composition different from the first barrier layer composition; and
a second fill material in the upper portion of the trench, the second fill material having a second fill material composition different from the first fill material composition.
2. The integrated circuit structure of claim 1 , wherein the first barrier layer comprises tantalum.
3. The integrated circuit structure of claim 1 , wherein the second barrier layer comprises ruthenium.
4. The integrated circuit structure of claim 1 , wherein the first barrier layer comprises tantalum, and wherein the second barrier layer comprises ruthenium.
5. The integrated circuit structure of claim 1 , wherein the first fill material comprises a metal selected from the group consisting of copper, aluminum and nickel.
6. The integrated circuit structure of claim 1 , wherein the second fill material comprises cobalt.
7. The integrated circuit structure of claim 1 , wherein the first fill material comprises a metal selected from the group consisting of copper, aluminum and nickel, and wherein the second fill material comprises cobalt.
8. The integrated circuit structure of claim 1 , wherein the dielectric layer further comprises an etch stop layer, the trench in the etch stop layer.
9. The integrated circuit structure of claim 1 , wherein the second barrier layer has a top surface co-planar with a top surface of the dielectric layer.
10. The integrated circuit structure of claim 1 , wherein the sidewalls of the trench are substantially vertical.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a dielectric layer;
a trench in the dielectric layer, the trench having a lower portion with sidewalls and an upper portion with sidewalls;
a first barrier layer along and in contact with the sidewalls of the lower portion of the trench, the first barrier layer having a first barrier layer composition;
a first fill material on the first barrier layer in the lower portion of the trench, the first fill material having a first fill material composition;
a second barrier layer along and in contact with the sidewalls of the upper portion of the trench, the second barrier layer having a second barrier layer composition different from the first barrier layer composition; and
a second fill material in the upper portion of the trench, the second fill material having a second fill material composition different from the first fill material composition.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a memory coupled to the board; and
a communication chip coupled to the board.
15. The computing device of claim 11 , further comprising:
a camera coupled to the board.
16. The computing device of claim 11 , further comprising:
a battery coupled to the board.
17. The computing device of claim 11 , further comprising:
an antenna coupled to the board.
18. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
19. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
20. The computing device of claim 11 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.