Increasing memory bandwidth in processor-based systems
View Patent ↗The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
1. A method comprising: transferring information between a processing unit and a memory during both the high and low phases of a clock, wherein the memory comprises a portion, wherein during any two consecutive phases of the clock, the portion can only be accessed once, latching any address lines that are not being addressed to avoid toggling and consuming dynamic power, using a first latch for data from a high phase write and a second latch for data from a low phase write, and dividing said memory into bundles, each bundle associated with a local bit line, a plurality of bundles associated with a global bit line, and avoid reading the same bundle in successive high and low phases.
2. The method of claim 1 including transferring information between a mathematical box and a general purpose register file during both the high and low phases of a clock.
3. The method of claim 1 including writing information to the memory during both the high and low phases of the clock.
4. The method of claim 1 including reading information from the memory during both the high and low phases of the clock.
5. The method of claim 1 including reading a first bank during a high phase of the clock and reading a second bank different from the first bank during a low phase of the clock.
6. The method of claim 5 including providing separate ports for each bank and using an OR gate to combine the signals for each port on the same address line.
7. The method of claim 6 including using the same address lines, but combining address ports for the low and high phase using an OR gate.
8. An apparatus comprising:
a memory having a portion;
a processing unit coupled to said memory;
said memory to read and write information during both the high and low phases of a clock, wherein during any two consecutive phases of the clock, said portion can only be accessed once;
a latch to latch any address line that is not being addressed in order to avoid toggling and consuming excessive dynamic power;
a first latch for data from the high phase “write and a second latch for data from a low phase write; and
said memory is divided into bundles, each bundle associated with a local bit line and a plurality of bundles associated with a global bit line, said memory to avoid reading the same bundle in successive high and low phases.
9. The apparatus of claim 8 wherein said memory is a general purpose register file.
10. The apparatus of claim 9 wherein said processing unit is a mathematical box.
11. The apparatus of claim 8 wherein said apparatus is a graphics processor.
12. The apparatus of claim 8 wherein said memory includes at least two banks of memory cells, said memory to read a first bank during a high phase of the clock and a second bank different from the first bank during the low phase of the clock.
13. The apparatus of claim 12 wherein said memory includes separate ports for each bank and an OR gate to combine the signals for each port on the same address line.
14. The apparatus of claim 13 , said memory including an OR gate to combine address ports for the low and high phase.