Memory receiver circuit for use with memory of different characteristics
View Patent ↗Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.
1. An apparatus comprising:
a differential amplifier coupled to a positive supply rail to receive a positive supply voltage (Vcc) and including circuitry to:
receive a data signal at an input terminal of the differential amplifier from a memory, the data signal having a first direct current (DC) average voltage level, wherein the data signal changes between a first voltage level to represent a first logical value and a second voltage level to represent a second logical value, and the first DC average voltage level is an average voltage of the first voltage level and the second voltage level;
pass a differential output signal at a pair of output terminals of the differential amplifier based on a voltage difference between the data signal and a reference voltage; and
shift the differential output signal to a second DC average voltage level, wherein the second DC average voltage level is substantially constant over a range of voltages of the first DC average voltage level, and wherein the second DC average voltage level is an average voltage of a third voltage level representing the first logical value and a fourth voltage level representing the second logical value.
2. The apparatus of claim 1 , wherein the differential amplifier is further coupled to a negative supply rail to receive a negative supply voltage (Vss), wherein the first DC average voltage level is referenced to the positive supply voltage and the second DC average voltage is referenced to the negative supply voltage.
3. The apparatus of claim 2 , wherein the negative supply voltage is a ground voltage, and the differential output signal is greater than zero if the data signal is greater than the reference voltage and less than zero if the data signal is less than the reference voltage.
4. The apparatus of claim 1 , wherein the memory is a dynamic random access memory (DRAM), wherein the apparatus is a first stage amplifier of a DRAM receiver, wherein the output terminals are coupled to a second stage amplifier of the DRAM receiver, and wherein the second stage amplifier is to operate using a power domain that is different from a power domain of the DRAM.
5. The apparatus of claim 1 , wherein the differential amplifier includes a differential pair of transistors with folded architecture, and wherein the apparatus further includes a bias circuit to generate a plurality of bias voltages for use by the differential amplifier to provide the differential output signal with the second DC average voltage level.
6. The apparatus of claim 1 , wherein the differential amplifier includes:
a first n-type transistor having a first gate, a first drain, and a first source, the first gate to receive the data signal;
a second n-type transistor having a second gate, a second drain, and a second source, wherein the second gate is to receive the reference voltage and the second source is coupled to the first source at a common node;
a controllable current source coupled between the common node and a ground terminal;
a first p-type transistor coupled to the first drain of the first n-type transistor;
a second p-type transistor coupled to the second drain of the second n-type transistor;
a first cascode transistor coupled between the first drain terminal and a first output terminal;
a second cascode transistor coupled between the second drain and a second output terminal, wherein the differential amplifier is to generate the differential output signal at the first and second output terminals;
a first load transistor coupled between the first output terminal and the ground terminal; and
a second load transistor coupled between the second output terminal and the ground terminal.
7. The apparatus of claim 6 , further comprising a bias circuit coupled to the differential amplifier to generate:
a control signal for the current source;
a pbias voltage for the first and second p-type transistors;
a cascode bias voltage for the first and second cascode transistors;
a load bias voltage for the first and second load transistors.
8. The apparatus of claim 1 , further comprising a voltage drop block coupled between the positive supply rail and the differential amplifier to selectively provide a voltage drop from the positive supply rail to the differential amplifier during a first mode.
9. The apparatus of claim 1 , wherein the memory is a dynamic random access memory (DRAM), and wherein the differential amplifier is to be used with DRAM in accordance with a double data rate (DDR) 3 protocol and with DRAM in accordance with a DDR4 protocol.
10. The apparatus of claim 1 , further comprising a voltage offset compensation (VOC) circuit coupled with the differential amplifier to add a compensation voltage to the differential output signal based on a rank or an identity of the memory.