Method for reducing power consumption in solid-state storage device
View Patent ↗Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD, while maintaining low resume latency upon exiting a reduced power state. By arranging a storage controller and at least one NAND flash package of the SSD in separate power islands, storing context information for the SSD in at least one page buffer of NAND flash memory within the NAND flash package on one power island upon entering the reduced power state, and, once the context information is stored in the page buffer, allowing the NAND flash memory to enter a standby mode, placing the storage controller on the other power island in a predefined low power mode, and removing power from any unneeded components on the same power island as the storage controller, a scalable approach to reducing idle power levels in the SSD can be achieved.
1. A method of reducing power consumption in a solid-state storage device, comprising:
providing a storage controller and a plurality of non-volatile memory packages, the storage controller and zero or more of the non-volatile memory packages being arranged on a first power island, and at least one of the non-volatile memory packages being arranged on a second power island;
upon entering a predetermined reduced power state of the solid-state storage device, storing, by the storage controller, context information for the solid-state storage device in at least one memory buffer within the non-volatile memory package on the second power island, and removing power from at least the non-volatile memory packages on the first power island; and
once the context information is stored in the memory buffer within the non-volatile memory package on the second power island, placing the non-volatile memory package on the second power island in a standby mode, and placing the storage controller on the first power island in a predefined low power mode.
2. The method of claim 1 further comprising:
in response to a predetermined event, exiting the storage controller from the predefined low power mode, and exiting the non-volatile memory package on the second power island from the standby mode.
3. The method of claim 2 further comprising:
applying power to the non-volatile memory packages on the first power island.
4. The method of claim 2 further comprising:
reading, by the storage controller, the context information from the memory buffer within the non-volatile memory package on the second power island.
5. The method of claim 4 further comprising:
storing, by the storage controller, the context information in volatile memory associated with the storage controller.
6. The method of claim 1 further comprising:
encoding, by an error checking and correction (ECC) encoder, the context information prior to storing the context information in the memory buffer within the non-volatile memory package on the second power island.
7. The method of claim 6 further comprising:
in response to a predetermined event, exiting the storage controller from the predefined low power mode, and exiting the non-volatile memory package on the second power island from the standby mode; and
reading, by the storage controller, the context information from the memory buffer within the non-volatile memory package on the second power island.
8. The method of claim 7 further comprising:
decoding the context information by an ECC decoder.
9. The method of claim 1 wherein the storing of the context information for the solid-state storage device includes storing some of the context information in volatile memory associated with the storage controller.
10. An apparatus for reducing power consumption in a solid-state storage device, comprising:
a storage controller;
a plurality of non-volatile memory packages,
wherein the storage controller and zero or more of the non-volatile memory packages are arranged on a first power island, and at least one of the non-volatile memory packages is arranged on a second power island; and
a power manager,
wherein, upon entering a predetermined reduced power state of the solid-state storage device:
the storage controller is operative to store context information for the solid-state storage device in at least one memory buffer within the non-volatile memory package on the second power island; and
the power manager is operative to remove power from at least the non-volatile memory packages on the first power island, and
wherein, once the context information is stored in the memory buffer within the non-volatile memory package on the second power island:
the non-volatile memory package on the second power island is operative to enter a standby mode, and
the storage controller on the first power island is operative to enter a predefined low power mode.
11. The apparatus of claim 10 wherein, in response to a predetermined event:
the storage controller is further operative to exit from the predefined low power mode, and
the non-volatile memory package on the second power island is further operative to exit from the standby mode.
12. The apparatus of claim 11 wherein the power manager is further operative to apply power to the non-volatile memory packages on the first power island.
13. The apparatus of claim 11 wherein the storage controller is further operative to read the context information from the memory buffer within the non-volatile memory package on the second power island.
14. The apparatus of claim 13 wherein the storage controller is further operative to store the context information in volatile memory associated with the storage controller.
15. The apparatus of claim 10 further comprising:
an error checking and correction (ECC) encoder operative to encode the context information prior to the context information being stored in the memory buffer within the non-volatile memory package on the second power island.
16. The apparatus of claim 15 :
wherein, in response to a predetermined event, the storage controller is further operative to exit from the predefined low power mode, and the non-volatile memory package on the second power island is further operative to exit from the standby mode; and
wherein the storage controller is further operative to read the context information from the memory buffer within the non-volatile memory package on the second power island.
17. The apparatus of claim 16 further comprising an ECC decoder operative to decode the context information.
18. The apparatus of claim 10 wherein the storage controller is further operative to store some of the context information in volatile memory associated with the storage controller.
19. A computer system, comprising:
a system bus;
a display communicably coupled to the system bus;
the apparatus of claim 10 communicably coupled to the system bus; and
at least one volatile memory coupled to the system bus.
20. The system of claim 19 wherein the apparatus is operative to store some of the context information in the volatile memory.