Selectable clocking synchronization of a parallel-to-serial converter and memory
View Patent ↗A technique includes providing a first clock signal to a parallel-to-serial data conversion circuit and providing a second clock signal to a memory storing data for conversion by the conversion circuit. One of the first and second clock signals is selectively synchronized to a reference clock signal.
1. A method comprising:
providing a first clock signal to a parallel-to-serial data conversion circuit;
providing a second clock signal to a memory storing data for conversion by the conversion circuit;
selectively synchronizing one of the first and second clock signals to a reference clock signal.
2. The method of claim 1 , further comprising:
synchronizing the other one of said one of the first and second clock signals to said one of the first and second clock signals.
3. The method of claim 1 , wherein selectively synchronizing comprises:
selectively placing the synchronization circuit in a first mode to synchronize the first clock signal to the reference clock signal and a second mode to synchronize the second clock signal to the reference clock signal.
4. The method of claim 1 , wherein selectively synchronizing comprises:
selectively providing one of the reference clock signal and an indication of the first clock signal to an input terminal of a phase locked loop circuit.
5. The method of claim 4 , wherein in response to providing the reference clock signal to the input terminal of the phase locked loop circuit, synchronizing the first clock signal to the reference clock signal.
6. The method of claim 5 , further comprising:
in response to providing the reference clock signal to the input terminal of the phase locked loop circuit, synchronize the second clock signal to the first clock signal.
7. The method of claim 4 , wherein in response to providing the indication of the first clock signal to the input terminal of the phase locked loop circuit, synchronizing the first clock signal to the second clock signal.
8. The method of claim 4 , wherein in response to providing the indication of the first clock signal to the input terminal of the phase locked loop circuit, synchronizing the second clock signal to the first clock signal.
9. An apparatus comprising:
a parallel-to-serial data conversion circuit to receive a first clock signal;
a memory storing data for conversion by the conversion circuit and receiving a second clock signal; and
a clock circuit to selectively synchronizing one of the first and second clock signals to a reference clock signal.
10. The apparatus of claim 9 , wherein the clock circuit comprises:
a phase locked loop circuit to synchronize the other one of said one of the first and second clock signals to said one of the first and second clock signals.
11. The apparatus of claim 9 , wherein the clock circuit has a first mode to synchronize the first clock signal to the reference clock signal and a second mode to synchronize the second clock signal to the reference clock signal.
12. The apparatus of claim 9 , wherein the clock circuit comprises:
a phase locked loop circuit to provide one of the first and second signals, and
selector circuitry to selectively provide one of a reference clock signal and an indication of the first clock signal to an input terminal of the phase locked loop circuit.
13. The apparatus of claim 12 , wherein the phase locked loop circuit provides the first clock signal and synchronizes the first clock signal to the reference clock signal in response to selector circuitry providing the reference clock signal to the input terminal of the phase locked loop circuit.
14. The apparatus of claim 12 , wherein the phase locked loop circuit provides the second clock signal and synchronizes the second clock signal to the first clock signal in response to the selector circuitry providing an indication of the first clock signal to the input terminal of the phase locked loop circuit.
15. The apparatus of claim 9 , wherein the parallel-to-serial conversion circuit provides a signal indicative of the data in synchronization with the first clock signal.
16. A system comprising:
a data source to provide data;
a bus;
a parallel-to-serial data conversion circuit to receive a first clock signal and generate a signal indicative of the data in a serial format in synchronization with the first clock signal;
a memory coupled to the data source to receive the data in a parallel format and communicate the data for conversion by the conversion circuit in synchronization with a second clock signal; and
a clock circuit to selectively synchronizing one of the first and second clock signals to a reference clock signal.
17. The system of claim 16 , wherein the clock circuit comprises:
a phase locked loop circuit to synchronize the other one of said one of the first and second clock signals to said one of the first and second clock signals.
18. The system of claim 16 , wherein the clock circuit has a first mode to synchronize the first clock signal to the reference clock signal and a second mode to synchronize the second clock signal to the reference clock signal.
19. The apparatus of claim 16 , wherein the clock circuit comprises:
a phase locked loop circuit to provide one of the first and second signals, and
selector circuitry to selectively provide one of a reference clock signal and an indication of the first clock signal to an input terminal of the phase locked loop circuit.
20. The system of claim 19 , wherein the phase locked loop circuit provides the first clock signal and synchronizes the first clock signal to the reference clock signal in response to selector circuitry providing the reference clock signal to the input terminal of the phase locked loop circuit.
21. The system of claim 19 , wherein the phase locked loop circuit provides the second clock signal and synchronizes the second clock signal to the first clock signal in response to the selector circuitry providing an indication of the first clock signal to the input terminal of the phase locked loop circuit.