Instruction for fast ZUC algorithm processing
Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
1. An apparatus comprising:
fetch circuitry to fetch instructions, including vector instructions;
decode circuitry to decode fetched instructions, including fetched vector instructions;
a plurality of vector registers; and
execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to:
receive a first decoded vector instruction to update a liner feedback shift register (LFSR) for stream cipher operations, wherein the first decoded vector instruction specifies two or more of the plurality of vector registers as operands;
receive a second decoded vector instruction to update a state of a finite state machine (FSM), wherein the FSM receives inputs from re-ordered bits of the LFSR, and wherein the second decoded vector instruction specifies two or more of the plurality of vector registers as operands; and
execute the first decoded vector instruction and the second decoded vector instruction in a single-instruction multiple data (SIMD) pipeline.
2. The apparatus of claim 1 ,
wherein the execution circuitry is further operative to:
receive a third decoded vector instruction to re-order the bits of the state of the LFSR.
3. The apparatus of claim 1 , wherein the second decoded vector instruction specifies a source operand that stores data elements of the LFSR needed for updating the FSM.
4. The apparatus of claim 1 , wherein the execution circuitry is further operative to:
execute the first decoded vector instruction and the second decoded vector instruction in a first phase that uses a first set of source operands;
execute the first decoded vector instruction and the second decoded vector instruction in a second phase that uses a second set of source operands; and
repeat the first phase and the second phase in a loop to generate a sequence of outputs for the stream cipher operations.
5. The apparatus of claim 1 , wherein the second decoded vector instruction is a SIMD instruction that updates two FSM state registers and generates an output for the stream cipher operations in parallel.
6. The apparatus of claim 5 , wherein the execution circuitry is further operative to:
update the two FSM state registers by applying a set of linear functions to the re-ordered bits of the state of the LFSR, wherein output of each linear function is formed by directly routing inputs of the linear function.
7. The apparatus of claim 1 , wherein the execution circuitry is further operative to:
execute multiple sets of the stream cipher operations in simultaneous streams of pipelining.
8. A method comprising:
fetching a first vector instruction and a second vector instruction;
decoding the first fetched vector instruction and the second fetched vector instruction;
receiving by execution circuitry the first decoded vector instruction, wherein the first decoded vector instruction is to update a liner feedback shift register (LFSR) for stream cipher operations;
receiving by execution circuitry the second decoded vector instruction, wherein the second decoded vector instruction is to update a state of a finite state machine (FSM), wherein the FSM receives inputs from re-ordered bits of the LFSR; and
executing the first decoded vector instruction and the second decoded vector instruction in a Single Instruction Multiple Data (SIMD) pipeline.
9. The method of claim 8 , further comprising:
fetching and decoding a third vector instruction;
receiving the third decoded vector instruction by the execution circuitry, wherein the third decoded vector instruction is to re-order the bits of the LFSR.
10. The method of claim 8 , wherein the second decoded vector instruction specifies a source operand that stores data elements of the LFSR needed for updating the FSM.
11. The method of claim 8 , further comprising:
executing the first decoded vector instruction and the second decoded vector instruction in a first phase that uses a first set of source operands;
executing the first decoded vector instruction and the second decoded vector instruction in a second phase that uses a second set of source operands; and
repeating the first phase and the second phase in a loop to generate a sequence of outputs for the stream cipher operations.
12. The method of claim 8 , wherein the second decoded vector instruction is a SIMD instruction that updates two FSM state registers and generates an output for the stream cipher operations in parallel.
13. The method of claim 12 , further comprising:
updating the two FSM state registers by applying a set of linear functions to the re-ordered bits of the state of the LFSR, wherein output of each linear function is formed by directly routing inputs of the linear function.
14. The method of claim 8 , further comprising:
executing multiple sets of the stream cipher operations in simultaneous streams of pipelining.
15. A system comprising:
memory; and
a processor coupled to the memory, the processor comprising:
fetch circuitry to fetch instructions, including vector instructions;
decode circuitry to decode fetched instructions, including fetched vector instructions;
a plurality of vector registers; and
execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to:
receive a first decoded vector instruction to update a liner feedback shift register (LFSR) for stream cipher operations, wherein the first decoded vector instruction specifies two or more of the plurality of vector registers as operands;
receive a second decoded vector instruction to update a state of a finite state machine (FSM), wherein the FSM receives inputs from re-ordered bits of the LFSR, and wherein the second decoded vector instruction specifies two or more of the plurality of vector registers as operands; and
execute the first decoded vector instruction and the second decoded vector instruction in a single-instruction multiple data (SIMD) pipeline.
16. The system of claim 15 , wherein the execution circuitry is further operative to:
receive a decoded third vector instruction to re-order the bits of the LFSR.
17. The system of claim 15 , wherein the second decoded vector instruction specifies a source operand that stores data elements of the LFSR needed for updating the FSM.
18. The system of claim 15 , wherein the execution circuitry is further operative to:
execute the first decoded vector instruction and the second decoded vector instruction in a first phase that uses a first set of source operands;
execute the first decoded vector instruction and the second decoded vector instruction in a second phase that uses a second set of source operands; and
repeat the first phase and the second phase in a loop to generate a sequence of outputs for the stream cipher operations.
19. The system of claim 15 , wherein the second decoded vector instruction is a SIMD instruction that updates two FSM state registers and generates an output for the stream cipher operations in parallel.
20. The system of claim 19 , wherein the execution circuitry is further operative to:
update the two FSM state registers by applying a set of linear functions to the re-ordered bits of the LFSR, wherein output of each linear function is formed by directly routing inputs of the linear function.
21. The system of claim 15 , wherein the execution circuitry is further operative to:
execute multiple sets of the stream cipher operations in simultaneous streams of pipelining.