Semi-volatile embedded memory with between-fin floating-gate device and method
Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.
1. An apparatus comprising:
a semiconductor substrate; and
a floating-gate memory structure formed on the semiconductor substrate, wherein the floating-gate memory structure includes a bitcell having:
a first fin structure extending from the substrate;
a second fin structure extending from the substrate;
a third fin structure extending from the substrate;
an oxide layer disposed between the first and second fin structures and between the second and third fin structures;
a gate of a first transistor, the gate disposed on the oxide layer and coupled with and extending over a top of the first fin structure;
a floating gate of a second transistor, the floating gate disposed on the oxide layer between the second and third fin structures;
a diffusion contact coupled with the first fin structure and the second fin structure;
a contact for a bitline coupled with the first fin structure; and
a contact for a source coupled with the third fin structure.
2. The apparatus of claim 1 , further comprising a logic structure formed on the semiconductor substrate and coupled with the floating-gate memory structure, wherein the logic structure includes a plurality of metal-oxide-semiconductor transistors.
3. The apparatus of claim 2 , wherein the logic structure is part of a processor.
4. The apparatus of claim 1 , wherein dimensions of the bitcell are 2.5 diffusion pitch by 1.5 polysilicon pitch.
5. The apparatus of claim 1 , wherein dimensions of the bitcell are 2 diffusion pitch by 2 polysilicon pitch.
6. The apparatus of claim 1 , wherein the first transistor is a P-type metal-oxide-semiconductor transistor.
7. The apparatus of claim 1 , wherein the first transistor is an N-type metal-oxide-semiconductor transistor.
8. The apparatus of claim 1 , further comprising a gate contact coupled with the gate, wherein the gate contact includes at least one of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al).
9. The apparatus of claim 1 , wherein the oxide layer below the floating gate is less than or equal to 3 nanometers equivalent oxide thickness.
10. An apparatus comprising:
a semiconductor substrate; and
a floating-gate memory structure formed on the semiconductor substrate, wherein the floating-gate memory structure includes a bitcell having:
a first fin structure extending from the substrate;
a second fin structure extending from the substrate;
a third fin structure extending from the substrate;
an oxide layer disposed between the first and second fin structures and between the second and third fin structures;
a gate of a first transistor, the gate disposed on the oxide layer and coupled with and extending over a top of the first fin structure;
a floating gate of a second transistor, the floating gate disposed on the oxide layer between the second and third fin structures;
a source line coupled with the first, second, and third fin structures at a first side of the bitcell; and
a contact for a bitline coupled with the second fin structure at a second side of the bitcell, wherein:
the gate extends over the top of the first, second, and third fin structures at a location between the contact for the bitline and the source line;
the floating gate is a first floating gate disposed between the second fin structure and the third fin structure at a location between the gate and the source line; and
the apparatus further includes a second floating gate of the second transistor disposed between the first fin structure and the second fin structure at a location between the gate and the source line.
11. The apparatus of claim 10 , further comprising a gate contact coupled with the gate, wherein the gate contact includes at least one of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al).
12. The apparatus of claim 10 , wherein the oxide layer below the floating gate is less than or equal to 3 nanometers equivalent oxide thickness.
13. The apparatus of claim 10 , further comprising a logic structure formed on the semiconductor substrate and coupled with the floating-gate memory structure, wherein the logic structure includes a plurality of metal-oxide-semiconductor transistors.
14. A method, comprising:
providing a semiconductor substrate; and
forming a floating-gate memory structure on the semiconductor substrate, wherein forming the floating-gate memory structure includes:
forming first, second, and third fin structures extending from the semiconductor substrate;
depositing an oxide layer between the first and second fin structures and between the second and third fin structures;
forming a gate of a first transistor, the gate disposed on the oxide layer and extending over a top of the first fin structure;
forming a floating gate of a second transistor, the floating gate disposed on the oxide layer between the second and third fin structures;
coupling a diffusion contact with the first fin structure and the second fin structure;
coupling a contact for a bitline with the first fin structure; and
coupling a contact for a source with the third fin structure.
15. The method of claim 14 , further comprising forming a logic structure on the semiconductor substrate coupled with the floating-gate memory structure, wherein the logic structure includes a plurality of metal-oxide-semiconductor transistors.
16. The method of claim 14 , wherein forming the floating-gate memory structure further includes coupling a gate contact with the gate, wherein the gate contact includes at least one of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al).
17. The method of claim 14 , wherein the oxide layer below the floating gate is less than or equal to 3 nanometers equivalent oxide thickness.
18. The method of claim 14 , wherein the gate is a polysilicon gate and forming the polysilicon gate and forming the floating gate includes:
forming a polysilicon gate layer that extends above the first, second, and third fin structures; and
removing a portion of the polysilicon gate layer above and between the second and third fin structures to form the floating gate between the second fin structure and the third fin structure,
wherein the polysilicon gate includes a portion of the polysilicon gate layer that was not removed from above the first fin structure.
19. A computing device comprising:
a semiconductor substrate;
a processor;
an output device coupled with the processor; and
a floating-gate memory structure coupled with the processor that includes a bitcell having:
a first fin structure extending from the semiconductor substrate;
a second fin structure extending from the semiconductor substrate;
a third fin structure extending from the semiconductor substrate;
an oxide layer disposed between the first and second fin structures and between the second and third fin structures;
a gate of a first transistor, the gate disposed on the oxide layer and coupled with and extending over a top of the first fin structure;
a floating gate of a second transistor, the floating gate disposed on the oxide layer between the second and third fin structures;
a diffusion contact coupled with the first fin structure and the second fin structure;
a contact for a bitline coupled with the first fin structure; and
a contact for a source coupled with the third fin structure.
20. The computing device of claim 19 , wherein the processor and the floating-gate memory structure are part of a system on a chip (SoC).
21. The computing device of claim 19 , wherein the floating-gate memory structure includes an array of bitcells accessed with a plurality of wordlines and a plurality of bitlines.
22. The computing device of claim 21 , wherein the array of bitcells includes a plurality of fin structures arranged in a plurality of rows, with every other fin structure having a contact for ground.
23. The computing device of claim 19 , wherein the bitcell further includes a gate contact coupled with the gate, wherein the gate includes at least one of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al).
24. The computing device of claim 19 , wherein the computing device is a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.